patch-2.4.10 linux/arch/mips/mm/mips32.c

• Lines: 69
• Date: Sun Sep 9 10:43:02 2001
• Orig file: v2.4.9/linux/arch/mips/mm/mips32.c
• Orig date: Wed Jul 25 17:10:18 2001

diff -u --recursive --new-file v2.4.9/linux/arch/mips/mm/mips32.c linux/arch/mips/mm/mips32.c
@@ -69,10 +69,8 @@
 {
 	unsigned long i;
 
-        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
-	{
-	        for (i=page; i<page+PAGE_SIZE; i+=dc_lsize)
-		{
+        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
+	        for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) {
 		        __asm__ __volatile__(
 			        ".set\tnoreorder\n\t"
 				".set\tnoat\n\t"
@@ -94,10 +92,8 @@
 {
 	unsigned long i;
 
-        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
-	{
-	        for (i=page; i<page+PAGE_SIZE; i+=sc_lsize)
-		{
+        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
+	        for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) {
 		        __asm__ __volatile__(
 				".set\tnoreorder\n\t"
 				".set\tnoat\n\t"
@@ -119,10 +115,8 @@
 {
 	unsigned long i;
 
-        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
-	{
-	        for (i=to; i<to+PAGE_SIZE; i+=dc_lsize)
-		{
+        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
+	        for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) {
 		        __asm__ __volatile__(
 			        ".set\tnoreorder\n\t"
 				".set\tnoat\n\t"
@@ -144,10 +138,8 @@
 {
 	unsigned long i;
 
-        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
-	{
-	        for (i=to; i<to+PAGE_SIZE; i+=sc_lsize)
-		{
+        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
+	        for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) {
 		        __asm__ __volatile__(
 				".set\tnoreorder\n\t"
 				".set\tnoat\n\t"
@@ -514,14 +506,8 @@
  */
 static void mips32_flush_cache_sigtramp(unsigned long addr)
 {
-	unsigned long daddr, iaddr;
-
-	daddr = addr & ~(dc_lsize - 1);
-	protected_writeback_dcache_line(daddr);
-	protected_writeback_dcache_line(daddr + dc_lsize);
-	iaddr = addr & ~(ic_lsize - 1);
-	protected_flush_icache_line(iaddr);
-	protected_flush_icache_line(iaddr + ic_lsize);
+	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+	protected_flush_icache_line(addr & ~(ic_lsize - 1));
 }
 
 #undef DEBUG_TLB