patch-2.4.5 linux/include/asm-ppc/keylargo.h

• Lines: 124
• Date: Mon May 21 15:02:06 2001
• Orig file: v2.4.4/linux/include/asm-ppc/keylargo.h
• Orig date: Mon Jan 22 15:41:15 2001

diff -u --recursive --new-file v2.4.4/linux/include/asm-ppc/keylargo.h linux/include/asm-ppc/keylargo.h
@@ -1,8 +1,17 @@
 /*
+ * BK Id: SCCS/s.keylargo.h 1.9 05/17/01 18:14:24 cort
+ */
+/*
  * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
  *
  */
 
+/* "Pangea" chipset has keylargo device-id 0x25 while core99
+ * has device-id 0x22. The rev. of the pangea one is 0, so we
+ * fake an artificial rev. in keylargo_rev by oring 0x100
+ */
+#define KL_PANGEA_REV		0x100
+
 /* offset from base for feature control registers */
 #define KEYLARGO_MBCR		0x34	/* Media bay control/status */
 #define KEYLARGO_FCR0		0x38
@@ -18,25 +27,47 @@
 #define KEYLARGO_GPIO_EXTINT_CNT	18
 #define KEYLARGO_GPIO_0			0x6A
 #define KEYLARGO_GPIO_CNT		17
+#define KEYLARGO_GPIO_OUTPUT_ENABLE	0x04
+#define KEYLARGO_GPIO_OUTOUT_DATA	0x01
 
 /* Specific GPIO regs */
 
+#define KL_GPIO_MODEM_RESET		(KEYLARGO_GPIO_0+0x03) /* Pangea */
+#define KL_GPIO_MODEM_POWER		(KEYLARGO_GPIO_0+0x02) /* Pangea */
+
+#define KL_GPIO_FW_CABLE_POWER		(KEYLARGO_GPIO_0+0x09)
+
 #define KL_GPIO_ETH_PHY_RESET		(KEYLARGO_GPIO_0+0x10)
-#define KL_GPIO_ETH_PHY_RESET_ASSERT	0x04
-#define KL_GPIO_ETH_PHY_RESET_RELEASE	0x05
-#define KL_GPIO_ETH_PHY_RESET_TRISTATE	0x00
-
-#define KL_GPIO_KICK_CPU1		(KEYLARGO_GPIO_0+0x0a)
-#define KL_GPIO_KICK_CPU1_UP		0x04
-#define KL_GPIO_KICK_CPU1_DOWN		0x38
+
+#define KL_GPIO_EXTINT_CPU1		(KEYLARGO_GPIO_0+0x0a)
+#define KL_GPIO_EXTINT_CPU1_ASSERT	0x04
+#define KL_GPIO_EXTINT_CPU1_RELEASE	0x38
+
+#define KL_GPIO_RESET_CPU0		(KEYLARGO_GPIO_EXTINT_0+0x03)
+#define KL_GPIO_RESET_CPU1		(KEYLARGO_GPIO_EXTINT_0+0x04)
+#define KL_GPIO_RESET_CPU2		(KEYLARGO_GPIO_EXTINT_0+0x0f)
+#define KL_GPIO_RESET_CPU3		(KEYLARGO_GPIO_EXTINT_0+0x10)
 
 #define KL_GPIO_PMU_MESSAGE_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x09)
 #define KL_GPIO_PMU_MESSAGE_BIT		0x02
 
+#define KL_GPIO_AIRPORT_0		(KEYLARGO_GPIO_EXTINT_0+0x0a)
+#define KL_GPIO_AIRPORT_1		(KEYLARGO_GPIO_EXTINT_0+0x0d)
+#define KL_GPIO_AIRPORT_2		(KEYLARGO_GPIO_0+0x0d)
+#define KL_GPIO_AIRPORT_3		(KEYLARGO_GPIO_0+0x0e)
+#define KL_GPIO_AIRPORT_4		(KEYLARGO_GPIO_0+0x0f)
+
 /*
  * Bits in feature control register
  */
-#define KL_MBCR_MBDEV_ENABLE		0x00001000
+#define KL_MBCR_MB0_DEV_ENABLE		0x00001000
+#define KL_MBCR_MB0_DEV_POWER		0x00000400
+#define KL_MBCR_MB0_DEV_RESET		0x00000200
+#define KL_MBCR_MB0_ENABLE		0x00000100
+#define KL_MBCR_MB1_DEV_ENABLE		0x10000000
+#define KL_MBCR_MB1_DEV_POWER		0x04000000
+#define KL_MBCR_MB1_DEV_RESET		0x02000000
+#define KL_MBCR_MB1_ENABLE		0x01000000
 
 #define KL0_SCC_B_INTF_ENABLE		0x00000001	/* ??? */
 #define KL0_SCC_A_INTF_ENABLE		0x00000002	/* ??? */
@@ -45,16 +76,27 @@
 #define KL0_SCCA_ENABLE			0x00000010
 #define KL0_SCCB_ENABLE			0x00000020
 #define KL0_SCC_CELL_ENABLE		0x00000040
-#define KL0_IRDA_ENABLE			0x00008000
-#define KL0_IRDA_CLK32_ENABLE		0x00010000
-#define KL0_IRDA_CLK19_ENABLE		0x00020000
 #define KL0_USB0_PAD_SUSPEND0		0x00040000
 #define KL0_USB0_PAD_SUSPEND1		0x00080000
 #define KL0_USB0_CELL_ENABLE		0x00100000
 #define KL0_USB1_PAD_SUSPEND0		0x00400000
 #define KL0_USB1_PAD_SUSPEND1		0x00800000
 #define KL0_USB1_CELL_ENABLE		0x01000000
+/* KL id 0x22 only */
 #define KL0_USB_REF_SUSPEND		0x10000000
+#define KL0_IRDA_ENABLE			0x00008000
+#define KL0_IRDA_CLK32_ENABLE		0x00010000
+#define KL0_IRDA_CLK19_ENABLE		0x00020000
+/* KL id 0x25 (pangea) only */
+#define KL0_USB1_PAD_SUSPEND_SEL	0x00020000
+#define KL0_USB1_REF_SUSPEND		0x00010000
+#define KL0_USB1_REF_SUSPEND_SEL	0x00008000
+#define KL0_USB1_PMI			0x00004000
+#define KL0_USB0_PAD_SUSPEND_SEL	0x00002000
+#define KL0_USB0_REF_SUSPEND		0x00001000
+#define KL0_USB0_REF_SUSPEND_SEL	0x00000800
+#define KL0_USB0_PMI			0x00000400
+
 
 #define KL0_SERIAL_ENABLE		(KL0_SCC_B_INTF_ENABLE | \
 					KL0_SCC_SLOWPCLK | \
@@ -102,11 +144,11 @@
 #define KL3_STOPPING33_ENABLED		0x00080000
 
 /* Port 0,1 : bus 0, port 2,3 : bus 1 */
-#define KL4_SET_PORT_ENABLE(p)		(0x00000008 << (p<<3))
-#define KL4_SET_PORT_RESUME(p)		(0x00000004 << (p<<3))
-#define KL4_SET_PORT_CONNECT(p)		(0x00000002 << (p<<3))
-#define KL4_SET_PORT_DISCONNECT(p)	(0x00000001 << (p<<3))
-#define KL4_GET_PORT_RESUME(p)		(0x00000040 << (p<<3))
-#define KL4_GET_PORT_CONNECT(p)		(0x00000020 << (p<<3))
-#define KL4_GET_PORT_DISCONNECT(p)	(0x00000010 << (p<<3))
+#define KL4_SET_PORT_ENABLE(p)		(0x00000008 << ((p)<<3))
+#define KL4_SET_PORT_RESUME(p)		(0x00000004 << ((p)<<3))
+#define KL4_SET_PORT_CONNECT(p)		(0x00000002 << ((p)<<3))
+#define KL4_SET_PORT_DISCONNECT(p)	(0x00000001 << ((p)<<3))
+#define KL4_GET_PORT_RESUME(p)		(0x00000040 << ((p)<<3))
+#define KL4_GET_PORT_CONNECT(p)		(0x00000020 << ((p)<<3))
+#define KL4_GET_PORT_DISCONNECT(p)	(0x00000010 << ((p)<<3))