patch-2.4.4 linux/include/asm-cris/sv_addr.agh

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diff -u --recursive --new-file v2.4.3/linux/include/asm-cris/sv_addr.agh linux/include/asm-cris/sv_addr.agh
@@ -1,8 +1,8 @@
 /*
 !* This file was automatically generated by /n/asic/bin/reg_macro_gen
-!* from the file `etrax_ng_regs.rd'.
+!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
 !* Editing within this file is thus not recommended,
-!* make the changes in `etrax_ng_regs.rd' instead.
+!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
 !*/
 
 
@@ -103,6 +103,10 @@
 #define R_BUS_STATUS__flashw__bw16 0
 
 #define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
+#define R_DRAM_TIMING__sdram__BITNR 31
+#define R_DRAM_TIMING__sdram__WIDTH 1
+#define R_DRAM_TIMING__sdram__enable 1
+#define R_DRAM_TIMING__sdram__disable 0
 #define R_DRAM_TIMING__ref__BITNR 14
 #define R_DRAM_TIMING__ref__WIDTH 2
 #define R_DRAM_TIMING__ref__e52us 0
@@ -683,10 +687,6 @@
 #define R_GEN_CONFIG__usb1__WIDTH 1
 #define R_GEN_CONFIG__usb1__select 1
 #define R_GEN_CONFIG__usb1__disable 0
-#define R_GEN_CONFIG__p21__BITNR 28
-#define R_GEN_CONFIG__p21__WIDTH 1
-#define R_GEN_CONFIG__p21__select 1
-#define R_GEN_CONFIG__p21__disable 0
 #define R_GEN_CONFIG__g24dir__BITNR 27
 #define R_GEN_CONFIG__g24dir__WIDTH 1
 #define R_GEN_CONFIG__g24dir__in 0
@@ -2331,6 +2331,10 @@
 #define R_NETWORK_GA_1__ga_high__WIDTH 32
 
 #define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
+#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
+#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
+#define R_NETWORK_REC_CONFIG__max_size__size1518 0
+#define R_NETWORK_REC_CONFIG__max_size__size1522 1
 #define R_NETWORK_REC_CONFIG__duplex__BITNR 9
 #define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
 #define R_NETWORK_REC_CONFIG__duplex__full 1
@@ -2535,6 +2539,10 @@
 #define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
 #define R_PAR0_STATUS_DATA__mode__ecp_rev 6
 #define R_PAR0_STATUS_DATA__mode__off 7
+#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
+#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
+#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
+#define R_PAR0_STATUS_DATA__mode__epp_rd 0
 #define R_PAR0_STATUS_DATA__perr__BITNR 28
 #define R_PAR0_STATUS_DATA__perr__WIDTH 1
 #define R_PAR0_STATUS_DATA__perr__active 1
@@ -2555,6 +2563,14 @@
 #define R_PAR0_STATUS_DATA__sel__WIDTH 1
 #define R_PAR0_STATUS_DATA__sel__active 1
 #define R_PAR0_STATUS_DATA__sel__inactive 0
+#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
+#define R_PAR0_STATUS_DATA__ext_mode__enable 1
+#define R_PAR0_STATUS_DATA__ext_mode__disable 0
+#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
+#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
+#define R_PAR0_STATUS_DATA__ecp_16__active 1
+#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
 #define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
 #define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
 #define R_PAR0_STATUS_DATA__tr_rdy__ready 1
@@ -2570,7 +2586,59 @@
 #define R_PAR0_STATUS_DATA__data__BITNR 0
 #define R_PAR0_STATUS_DATA__data__WIDTH 8
 
-#define R_PAR_ECP16_DATA (IO_TYPECAST_RO_UWORD 0xb0000040)
+#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
+#define R_PAR0_STATUS__mode__BITNR 13
+#define R_PAR0_STATUS__mode__WIDTH 3
+#define R_PAR0_STATUS__mode__manual 0
+#define R_PAR0_STATUS__mode__centronics 1
+#define R_PAR0_STATUS__mode__fastbyte 2
+#define R_PAR0_STATUS__mode__nibble 3
+#define R_PAR0_STATUS__mode__byte 4
+#define R_PAR0_STATUS__mode__ecp_fwd 5
+#define R_PAR0_STATUS__mode__ecp_rev 6
+#define R_PAR0_STATUS__mode__off 7
+#define R_PAR0_STATUS__mode__epp_wr1 5
+#define R_PAR0_STATUS__mode__epp_wr2 6
+#define R_PAR0_STATUS__mode__epp_wr3 7
+#define R_PAR0_STATUS__mode__epp_rd 0
+#define R_PAR0_STATUS__perr__BITNR 12
+#define R_PAR0_STATUS__perr__WIDTH 1
+#define R_PAR0_STATUS__perr__active 1
+#define R_PAR0_STATUS__perr__inactive 0
+#define R_PAR0_STATUS__ack__BITNR 11
+#define R_PAR0_STATUS__ack__WIDTH 1
+#define R_PAR0_STATUS__ack__active 0
+#define R_PAR0_STATUS__ack__inactive 1
+#define R_PAR0_STATUS__busy__BITNR 10
+#define R_PAR0_STATUS__busy__WIDTH 1
+#define R_PAR0_STATUS__busy__active 1
+#define R_PAR0_STATUS__busy__inactive 0
+#define R_PAR0_STATUS__fault__BITNR 9
+#define R_PAR0_STATUS__fault__WIDTH 1
+#define R_PAR0_STATUS__fault__active 0
+#define R_PAR0_STATUS__fault__inactive 1
+#define R_PAR0_STATUS__sel__BITNR 8
+#define R_PAR0_STATUS__sel__WIDTH 1
+#define R_PAR0_STATUS__sel__active 1
+#define R_PAR0_STATUS__sel__inactive 0
+#define R_PAR0_STATUS__ext_mode__BITNR 7
+#define R_PAR0_STATUS__ext_mode__WIDTH 1
+#define R_PAR0_STATUS__ext_mode__enable 1
+#define R_PAR0_STATUS__ext_mode__disable 0
+#define R_PAR0_STATUS__ecp_16__BITNR 6
+#define R_PAR0_STATUS__ecp_16__WIDTH 1
+#define R_PAR0_STATUS__ecp_16__active 1
+#define R_PAR0_STATUS__ecp_16__inactive 0
+#define R_PAR0_STATUS__tr_rdy__BITNR 1
+#define R_PAR0_STATUS__tr_rdy__WIDTH 1
+#define R_PAR0_STATUS__tr_rdy__ready 1
+#define R_PAR0_STATUS__tr_rdy__busy 0
+#define R_PAR0_STATUS__dav__BITNR 0
+#define R_PAR0_STATUS__dav__WIDTH 1
+#define R_PAR0_STATUS__dav__data 1
+#define R_PAR0_STATUS__dav__nodata 0
+
+#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
 #define R_PAR_ECP16_DATA__data__BITNR 0
 #define R_PAR_ECP16_DATA__data__WIDTH 16
 
@@ -2669,6 +2737,10 @@
 #define R_PAR0_CONFIG__mode__ecp_fwd 5
 #define R_PAR0_CONFIG__mode__ecp_rev 6
 #define R_PAR0_CONFIG__mode__off 7
+#define R_PAR0_CONFIG__mode__epp_wr1 5
+#define R_PAR0_CONFIG__mode__epp_wr2 6
+#define R_PAR0_CONFIG__mode__epp_wr3 7
+#define R_PAR0_CONFIG__mode__epp_rd 0
 
 #define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
 #define R_PAR0_DELAY__fine_hold__BITNR 21
@@ -2731,6 +2803,10 @@
 #define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
 #define R_PAR1_STATUS_DATA__mode__ecp_rev 6
 #define R_PAR1_STATUS_DATA__mode__off 7
+#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
+#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
+#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
+#define R_PAR1_STATUS_DATA__mode__epp_rd 0
 #define R_PAR1_STATUS_DATA__perr__BITNR 28
 #define R_PAR1_STATUS_DATA__perr__WIDTH 1
 #define R_PAR1_STATUS_DATA__perr__active 1
@@ -2751,6 +2827,10 @@
 #define R_PAR1_STATUS_DATA__sel__WIDTH 1
 #define R_PAR1_STATUS_DATA__sel__active 1
 #define R_PAR1_STATUS_DATA__sel__inactive 0
+#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
+#define R_PAR1_STATUS_DATA__ext_mode__enable 1
+#define R_PAR1_STATUS_DATA__ext_mode__disable 0
 #define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
 #define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
 #define R_PAR1_STATUS_DATA__tr_rdy__ready 1
@@ -2766,6 +2846,54 @@
 #define R_PAR1_STATUS_DATA__data__BITNR 0
 #define R_PAR1_STATUS_DATA__data__WIDTH 8
 
+#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
+#define R_PAR1_STATUS__mode__BITNR 13
+#define R_PAR1_STATUS__mode__WIDTH 3
+#define R_PAR1_STATUS__mode__manual 0
+#define R_PAR1_STATUS__mode__centronics 1
+#define R_PAR1_STATUS__mode__fastbyte 2
+#define R_PAR1_STATUS__mode__nibble 3
+#define R_PAR1_STATUS__mode__byte 4
+#define R_PAR1_STATUS__mode__ecp_fwd 5
+#define R_PAR1_STATUS__mode__ecp_rev 6
+#define R_PAR1_STATUS__mode__off 7
+#define R_PAR1_STATUS__mode__epp_wr1 5
+#define R_PAR1_STATUS__mode__epp_wr2 6
+#define R_PAR1_STATUS__mode__epp_wr3 7
+#define R_PAR1_STATUS__mode__epp_rd 0
+#define R_PAR1_STATUS__perr__BITNR 12
+#define R_PAR1_STATUS__perr__WIDTH 1
+#define R_PAR1_STATUS__perr__active 1
+#define R_PAR1_STATUS__perr__inactive 0
+#define R_PAR1_STATUS__ack__BITNR 11
+#define R_PAR1_STATUS__ack__WIDTH 1
+#define R_PAR1_STATUS__ack__active 0
+#define R_PAR1_STATUS__ack__inactive 1
+#define R_PAR1_STATUS__busy__BITNR 10
+#define R_PAR1_STATUS__busy__WIDTH 1
+#define R_PAR1_STATUS__busy__active 1
+#define R_PAR1_STATUS__busy__inactive 0
+#define R_PAR1_STATUS__fault__BITNR 9
+#define R_PAR1_STATUS__fault__WIDTH 1
+#define R_PAR1_STATUS__fault__active 0
+#define R_PAR1_STATUS__fault__inactive 1
+#define R_PAR1_STATUS__sel__BITNR 8
+#define R_PAR1_STATUS__sel__WIDTH 1
+#define R_PAR1_STATUS__sel__active 1
+#define R_PAR1_STATUS__sel__inactive 0
+#define R_PAR1_STATUS__ext_mode__BITNR 7
+#define R_PAR1_STATUS__ext_mode__WIDTH 1
+#define R_PAR1_STATUS__ext_mode__enable 1
+#define R_PAR1_STATUS__ext_mode__disable 0
+#define R_PAR1_STATUS__tr_rdy__BITNR 1
+#define R_PAR1_STATUS__tr_rdy__WIDTH 1
+#define R_PAR1_STATUS__tr_rdy__ready 1
+#define R_PAR1_STATUS__tr_rdy__busy 0
+#define R_PAR1_STATUS__dav__BITNR 0
+#define R_PAR1_STATUS__dav__WIDTH 1
+#define R_PAR1_STATUS__dav__data 1
+#define R_PAR1_STATUS__dav__nodata 0
+
 #define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
 #define R_PAR1_CONFIG__ioe__BITNR 25
 #define R_PAR1_CONFIG__ioe__WIDTH 1
@@ -2857,6 +2985,10 @@
 #define R_PAR1_CONFIG__mode__ecp_fwd 5
 #define R_PAR1_CONFIG__mode__ecp_rev 6
 #define R_PAR1_CONFIG__mode__off 7
+#define R_PAR1_CONFIG__mode__epp_wr1 5
+#define R_PAR1_CONFIG__mode__epp_wr2 6
+#define R_PAR1_CONFIG__mode__epp_wr3 7
+#define R_PAR1_CONFIG__mode__epp_rd 0
 
 #define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
 #define R_PAR1_DELAY__fine_hold__BITNR 21
@@ -3437,10 +3569,6 @@
 #define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
 #define R_IRQ_MASK0_RD__ata_irq2__active 1
 #define R_IRQ_MASK0_RD__ata_irq2__inactive 0
-#define R_IRQ_MASK0_RD__p21_irq2__BITNR 10
-#define R_IRQ_MASK0_RD__p21_irq2__WIDTH 1
-#define R_IRQ_MASK0_RD__p21_irq2__active 1
-#define R_IRQ_MASK0_RD__p21_irq2__inactive 0
 #define R_IRQ_MASK0_RD__par0_data__BITNR 9
 #define R_IRQ_MASK0_RD__par0_data__WIDTH 1
 #define R_IRQ_MASK0_RD__par0_data__active 1
@@ -3449,10 +3577,6 @@
 #define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
 #define R_IRQ_MASK0_RD__ata_irq1__active 1
 #define R_IRQ_MASK0_RD__ata_irq1__inactive 0
-#define R_IRQ_MASK0_RD__p21_irq1__BITNR 9
-#define R_IRQ_MASK0_RD__p21_irq1__WIDTH 1
-#define R_IRQ_MASK0_RD__p21_irq1__active 1
-#define R_IRQ_MASK0_RD__p21_irq1__inactive 0
 #define R_IRQ_MASK0_RD__par0_ready__BITNR 8
 #define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
 #define R_IRQ_MASK0_RD__par0_ready__active 1
@@ -3469,10 +3593,6 @@
 #define R_IRQ_MASK0_RD__scsi0__WIDTH 1
 #define R_IRQ_MASK0_RD__scsi0__active 1
 #define R_IRQ_MASK0_RD__scsi0__inactive 0
-#define R_IRQ_MASK0_RD__p21_irq0__BITNR 8
-#define R_IRQ_MASK0_RD__p21_irq0__WIDTH 1
-#define R_IRQ_MASK0_RD__p21_irq0__active 1
-#define R_IRQ_MASK0_RD__p21_irq0__inactive 0
 #define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
 #define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
 #define R_IRQ_MASK0_RD__ata_dmaend__active 1
@@ -3599,10 +3719,6 @@
 #define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
 #define R_IRQ_MASK0_CLR__ata_irq2__clr 1
 #define R_IRQ_MASK0_CLR__ata_irq2__nop 0
-#define R_IRQ_MASK0_CLR__p21_irq2__BITNR 10
-#define R_IRQ_MASK0_CLR__p21_irq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__p21_irq2__clr 1
-#define R_IRQ_MASK0_CLR__p21_irq2__nop 0
 #define R_IRQ_MASK0_CLR__par0_data__BITNR 9
 #define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
 #define R_IRQ_MASK0_CLR__par0_data__clr 1
@@ -3611,10 +3727,6 @@
 #define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
 #define R_IRQ_MASK0_CLR__ata_irq1__clr 1
 #define R_IRQ_MASK0_CLR__ata_irq1__nop 0
-#define R_IRQ_MASK0_CLR__p21_irq1__BITNR 9
-#define R_IRQ_MASK0_CLR__p21_irq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__p21_irq1__clr 1
-#define R_IRQ_MASK0_CLR__p21_irq1__nop 0
 #define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
 #define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
 #define R_IRQ_MASK0_CLR__par0_ready__clr 1
@@ -3631,10 +3743,6 @@
 #define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
 #define R_IRQ_MASK0_CLR__scsi0__clr 1
 #define R_IRQ_MASK0_CLR__scsi0__nop 0
-#define R_IRQ_MASK0_CLR__p21_irq0__BITNR 8
-#define R_IRQ_MASK0_CLR__p21_irq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__p21_irq0__clr 1
-#define R_IRQ_MASK0_CLR__p21_irq0__nop 0
 #define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
 #define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
 #define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
@@ -3761,10 +3869,6 @@
 #define R_IRQ_READ0__ata_irq2__WIDTH 1
 #define R_IRQ_READ0__ata_irq2__active 1
 #define R_IRQ_READ0__ata_irq2__inactive 0
-#define R_IRQ_READ0__p21_irq2__BITNR 10
-#define R_IRQ_READ0__p21_irq2__WIDTH 1
-#define R_IRQ_READ0__p21_irq2__active 1
-#define R_IRQ_READ0__p21_irq2__inactive 0
 #define R_IRQ_READ0__par0_data__BITNR 9
 #define R_IRQ_READ0__par0_data__WIDTH 1
 #define R_IRQ_READ0__par0_data__active 1
@@ -3773,10 +3877,6 @@
 #define R_IRQ_READ0__ata_irq1__WIDTH 1
 #define R_IRQ_READ0__ata_irq1__active 1
 #define R_IRQ_READ0__ata_irq1__inactive 0
-#define R_IRQ_READ0__p21_irq1__BITNR 9
-#define R_IRQ_READ0__p21_irq1__WIDTH 1
-#define R_IRQ_READ0__p21_irq1__active 1
-#define R_IRQ_READ0__p21_irq1__inactive 0
 #define R_IRQ_READ0__par0_ready__BITNR 8
 #define R_IRQ_READ0__par0_ready__WIDTH 1
 #define R_IRQ_READ0__par0_ready__active 1
@@ -3793,10 +3893,6 @@
 #define R_IRQ_READ0__scsi0__WIDTH 1
 #define R_IRQ_READ0__scsi0__active 1
 #define R_IRQ_READ0__scsi0__inactive 0
-#define R_IRQ_READ0__p21_irq0__BITNR 8
-#define R_IRQ_READ0__p21_irq0__WIDTH 1
-#define R_IRQ_READ0__p21_irq0__active 1
-#define R_IRQ_READ0__p21_irq0__inactive 0
 #define R_IRQ_READ0__ata_dmaend__BITNR 7
 #define R_IRQ_READ0__ata_dmaend__WIDTH 1
 #define R_IRQ_READ0__ata_dmaend__active 1
@@ -3923,10 +4019,6 @@
 #define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
 #define R_IRQ_MASK0_SET__ata_irq2__set 1
 #define R_IRQ_MASK0_SET__ata_irq2__nop 0
-#define R_IRQ_MASK0_SET__p21_irq2__BITNR 10
-#define R_IRQ_MASK0_SET__p21_irq2__WIDTH 1
-#define R_IRQ_MASK0_SET__p21_irq2__set 1
-#define R_IRQ_MASK0_SET__p21_irq2__nop 0
 #define R_IRQ_MASK0_SET__par0_data__BITNR 9
 #define R_IRQ_MASK0_SET__par0_data__WIDTH 1
 #define R_IRQ_MASK0_SET__par0_data__set 1
@@ -3935,10 +4027,6 @@
 #define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
 #define R_IRQ_MASK0_SET__ata_irq1__set 1
 #define R_IRQ_MASK0_SET__ata_irq1__nop 0
-#define R_IRQ_MASK0_SET__p21_irq1__BITNR 9
-#define R_IRQ_MASK0_SET__p21_irq1__WIDTH 1
-#define R_IRQ_MASK0_SET__p21_irq1__set 1
-#define R_IRQ_MASK0_SET__p21_irq1__nop 0
 #define R_IRQ_MASK0_SET__par0_ready__BITNR 8
 #define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
 #define R_IRQ_MASK0_SET__par0_ready__set 1
@@ -3955,10 +4043,6 @@
 #define R_IRQ_MASK0_SET__scsi0__WIDTH 1
 #define R_IRQ_MASK0_SET__scsi0__set 1
 #define R_IRQ_MASK0_SET__scsi0__nop 0
-#define R_IRQ_MASK0_SET__p21_irq0__BITNR 8
-#define R_IRQ_MASK0_SET__p21_irq0__WIDTH 1
-#define R_IRQ_MASK0_SET__p21_irq0__set 1
-#define R_IRQ_MASK0_SET__p21_irq0__nop 0
 #define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
 #define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
 #define R_IRQ_MASK0_SET__ata_dmaend__set 1
@@ -4953,10 +5037,6 @@
 #define R_VECT_MASK_RD__mio__WIDTH 1
 #define R_VECT_MASK_RD__mio__active 1
 #define R_VECT_MASK_RD__mio__inactive 0
-#define R_VECT_MASK_RD__p21__BITNR 4
-#define R_VECT_MASK_RD__p21__WIDTH 1
-#define R_VECT_MASK_RD__p21__active 1
-#define R_VECT_MASK_RD__p21__inactive 0
 #define R_VECT_MASK_RD__timer1__BITNR 3
 #define R_VECT_MASK_RD__timer1__WIDTH 1
 #define R_VECT_MASK_RD__timer1__active 1
@@ -5075,10 +5155,6 @@
 #define R_VECT_MASK_CLR__mio__WIDTH 1
 #define R_VECT_MASK_CLR__mio__clr 1
 #define R_VECT_MASK_CLR__mio__nop 0
-#define R_VECT_MASK_CLR__p21__BITNR 4
-#define R_VECT_MASK_CLR__p21__WIDTH 1
-#define R_VECT_MASK_CLR__p21__clr 1
-#define R_VECT_MASK_CLR__p21__nop 0
 #define R_VECT_MASK_CLR__timer1__BITNR 3
 #define R_VECT_MASK_CLR__timer1__WIDTH 1
 #define R_VECT_MASK_CLR__timer1__clr 1
@@ -5197,10 +5273,6 @@
 #define R_VECT_READ__mio__WIDTH 1
 #define R_VECT_READ__mio__active 1
 #define R_VECT_READ__mio__inactive 0
-#define R_VECT_READ__p21__BITNR 4
-#define R_VECT_READ__p21__WIDTH 1
-#define R_VECT_READ__p21__active 1
-#define R_VECT_READ__p21__inactive 0
 #define R_VECT_READ__timer1__BITNR 3
 #define R_VECT_READ__timer1__WIDTH 1
 #define R_VECT_READ__timer1__active 1
@@ -5319,10 +5391,6 @@
 #define R_VECT_MASK_SET__mio__WIDTH 1
 #define R_VECT_MASK_SET__mio__set 1
 #define R_VECT_MASK_SET__mio__nop 0
-#define R_VECT_MASK_SET__p21__BITNR 4
-#define R_VECT_MASK_SET__p21__WIDTH 1
-#define R_VECT_MASK_SET__p21__set 1
-#define R_VECT_MASK_SET__p21__nop 0
 #define R_VECT_MASK_SET__timer1__BITNR 3
 #define R_VECT_MASK_SET__timer1__WIDTH 1
 #define R_VECT_MASK_SET__timer1__set 1
@@ -5997,6 +6065,10 @@
 #define R_USB_COMMAND__port_cmd__disable 1
 #define R_USB_COMMAND__port_cmd__suspend 2
 #define R_USB_COMMAND__port_cmd__resume 3
+#define R_USB_COMMAND__busy__BITNR 3
+#define R_USB_COMMAND__busy__WIDTH 1
+#define R_USB_COMMAND__busy__no 0
+#define R_USB_COMMAND__busy__yes 1
 #define R_USB_COMMAND__ctrl_cmd__BITNR 0
 #define R_USB_COMMAND__ctrl_cmd__WIDTH 3
 #define R_USB_COMMAND__ctrl_cmd__nop 0
@@ -6004,15 +6076,47 @@
 #define R_USB_COMMAND__ctrl_cmd__deconfig 2
 #define R_USB_COMMAND__ctrl_cmd__host_config 3
 #define R_USB_COMMAND__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND__ctrl_cmd__host_reset 5
+#define R_USB_COMMAND__ctrl_cmd__host_nop 5
 #define R_USB_COMMAND__ctrl_cmd__host_run 6
 #define R_USB_COMMAND__ctrl_cmd__host_stop 7
 
+#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
+#define R_USB_COMMAND_DEV__port_sel__BITNR 6
+#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
+#define R_USB_COMMAND_DEV__port_sel__nop 0
+#define R_USB_COMMAND_DEV__port_sel__dummy1 1
+#define R_USB_COMMAND_DEV__port_sel__dummy2 2
+#define R_USB_COMMAND_DEV__port_sel__any 3
+#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
+#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
+#define R_USB_COMMAND_DEV__port_cmd__active 0
+#define R_USB_COMMAND_DEV__port_cmd__passive 1
+#define R_USB_COMMAND_DEV__port_cmd__nop 2
+#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
+#define R_USB_COMMAND_DEV__busy__BITNR 3
+#define R_USB_COMMAND_DEV__busy__WIDTH 1
+#define R_USB_COMMAND_DEV__busy__no 0
+#define R_USB_COMMAND_DEV__busy__yes 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
+#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
+#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
+#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7
+
 #define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
-#define R_USB_STATUS__busy__BITNR 7
-#define R_USB_STATUS__busy__WIDTH 1
-#define R_USB_STATUS__busy__no 0
-#define R_USB_STATUS__busy__yes 1
+#define R_USB_STATUS__ourun__BITNR 5
+#define R_USB_STATUS__ourun__WIDTH 1
+#define R_USB_STATUS__ourun__no 0
+#define R_USB_STATUS__ourun__yes 1
+#define R_USB_STATUS__perror__BITNR 4
+#define R_USB_STATUS__perror__WIDTH 1
+#define R_USB_STATUS__perror__no 0
+#define R_USB_STATUS__perror__yes 1
 #define R_USB_STATUS__device_mode__BITNR 3
 #define R_USB_STATUS__device_mode__WIDTH 1
 #define R_USB_STATUS__device_mode__no 0
@@ -6031,30 +6135,34 @@
 #define R_USB_STATUS__running__yes 1
 
 #define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 13
-#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eof__set 1
-#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 12
+#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
 #define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
 #define R_USB_IRQ_MASK_SET__iso_eof__nop 0
 #define R_USB_IRQ_MASK_SET__iso_eof__set 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
-#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eot__set 1
-#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eof__set 1
+#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
 #define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
 #define R_USB_IRQ_MASK_SET__iso_eot__nop 0
 #define R_USB_IRQ_MASK_SET__iso_eot__set 1
+#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eot__set 1
+#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
+#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
+#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET__epid_attn__set 1
 #define R_USB_IRQ_MASK_SET__sof__BITNR 2
 #define R_USB_IRQ_MASK_SET__sof__WIDTH 1
 #define R_USB_IRQ_MASK_SET__sof__nop 0
@@ -6069,30 +6177,34 @@
 #define R_USB_IRQ_MASK_SET__ctl_status__set 1
 
 #define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 13
-#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
-#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 12
+#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
 #define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
 #define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
 #define R_USB_IRQ_MASK_READ__iso_eof__pend 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
-#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
+#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
 #define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
 #define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
 #define R_USB_IRQ_MASK_READ__iso_eot__pend 1
+#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
+#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
+#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
+#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
 #define R_USB_IRQ_MASK_READ__sof__BITNR 2
 #define R_USB_IRQ_MASK_READ__sof__WIDTH 1
 #define R_USB_IRQ_MASK_READ__sof__no_pend 0
@@ -6107,30 +6219,34 @@
 #define R_USB_IRQ_MASK_READ__ctl_status__pend 1
 
 #define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 13
-#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 12
+#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
 #define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
 #define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
 #define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
+#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
 #define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
 #define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
 #define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
 #define R_USB_IRQ_MASK_CLR__sof__BITNR 2
 #define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
 #define R_USB_IRQ_MASK_CLR__sof__nop 0
@@ -6145,30 +6261,34 @@
 #define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
 
 #define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ__intr_eof__BITNR 13
-#define R_USB_IRQ_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_READ__intr_eof__pend 1
-#define R_USB_IRQ_READ__iso_eof__BITNR 12
+#define R_USB_IRQ_READ__iso_eof__BITNR 13
 #define R_USB_IRQ_READ__iso_eof__WIDTH 1
 #define R_USB_IRQ_READ__iso_eof__no_pend 0
 #define R_USB_IRQ_READ__iso_eof__pend 1
-#define R_USB_IRQ_READ__bulk_eot__BITNR 11
-#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_READ__bulk_eot__pend 1
-#define R_USB_IRQ_READ__ctl_eot__BITNR 10
-#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_READ__ctl_eot__pend 1
-#define R_USB_IRQ_READ__intr_eot__BITNR 9
-#define R_USB_IRQ_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_READ__intr_eot__pend 1
-#define R_USB_IRQ_READ__iso_eot__BITNR 8
+#define R_USB_IRQ_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_READ__intr_eof__WIDTH 1
+#define R_USB_IRQ_READ__intr_eof__no_pend 0
+#define R_USB_IRQ_READ__intr_eof__pend 1
+#define R_USB_IRQ_READ__iso_eot__BITNR 11
 #define R_USB_IRQ_READ__iso_eot__WIDTH 1
 #define R_USB_IRQ_READ__iso_eot__no_pend 0
 #define R_USB_IRQ_READ__iso_eot__pend 1
+#define R_USB_IRQ_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_READ__intr_eot__WIDTH 1
+#define R_USB_IRQ_READ__intr_eot__no_pend 0
+#define R_USB_IRQ_READ__intr_eot__pend 1
+#define R_USB_IRQ_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
+#define R_USB_IRQ_READ__ctl_eot__no_pend 0
+#define R_USB_IRQ_READ__ctl_eot__pend 1
+#define R_USB_IRQ_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
+#define R_USB_IRQ_READ__bulk_eot__no_pend 0
+#define R_USB_IRQ_READ__bulk_eot__pend 1
+#define R_USB_IRQ_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_READ__epid_attn__WIDTH 1
+#define R_USB_IRQ_READ__epid_attn__no_pend 0
+#define R_USB_IRQ_READ__epid_attn__pend 1
 #define R_USB_IRQ_READ__sof__BITNR 2
 #define R_USB_IRQ_READ__sof__WIDTH 1
 #define R_USB_IRQ_READ__sof__no_pend 0
@@ -6182,7 +6302,159 @@
 #define R_USB_IRQ_READ__ctl_status__no_pend 0
 #define R_USB_IRQ_READ__ctl_status__pend 1
 
-#define R_USB_FM_NUMBER (IO_TYPECAST_RO_UDWORD 0xb000020c)
+#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
+#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
+
+#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
+
+#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
+
+#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
+#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__out_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
+#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
+#define R_USB_IRQ_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
+#define R_USB_IRQ_READ_DEV__sof__no_pend 0
+#define R_USB_IRQ_READ_DEV__sof__pend 1
+#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__port_status__pend 1
+#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
+
+#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
 #define R_USB_FM_NUMBER__value__BITNR 0
 #define R_USB_FM_NUMBER__value__WIDTH 32
 
@@ -6200,22 +6472,26 @@
 #define R_USB_FM_PSTART__value__BITNR 0
 #define R_USB_FM_PSTART__value__WIDTH 14
 
-#define R_USB_LS_THRESHOLD (IO_TYPECAST_UWORD 0xb0000216)
-#define R_USB_LS_THRESHOLD__value__BITNR 0
-#define R_USB_LS_THRESHOLD__value__WIDTH 14
-
 #define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
+#define R_USB_RH_STATUS__babble2__BITNR 7
+#define R_USB_RH_STATUS__babble2__WIDTH 1
+#define R_USB_RH_STATUS__babble2__no 0
+#define R_USB_RH_STATUS__babble2__yes 1
+#define R_USB_RH_STATUS__babble1__BITNR 6
+#define R_USB_RH_STATUS__babble1__WIDTH 1
+#define R_USB_RH_STATUS__babble1__no 0
+#define R_USB_RH_STATUS__babble1__yes 1
 #define R_USB_RH_STATUS__bus1__BITNR 4
 #define R_USB_RH_STATUS__bus1__WIDTH 2
 #define R_USB_RH_STATUS__bus1__SE0 0
 #define R_USB_RH_STATUS__bus1__Diff0 1
-#define R_USB_RH_STATUS__bus1__Diff1 1
+#define R_USB_RH_STATUS__bus1__Diff1 2
 #define R_USB_RH_STATUS__bus1__SE1 3
 #define R_USB_RH_STATUS__bus2__BITNR 2
 #define R_USB_RH_STATUS__bus2__WIDTH 2
 #define R_USB_RH_STATUS__bus2__SE0 0
 #define R_USB_RH_STATUS__bus2__Diff0 1
-#define R_USB_RH_STATUS__bus2__Diff1 1
+#define R_USB_RH_STATUS__bus2__Diff1 2
 #define R_USB_RH_STATUS__bus2__SE1 3
 #define R_USB_RH_STATUS__nports__BITNR 0
 #define R_USB_RH_STATUS__nports__WIDTH 2
@@ -6231,10 +6507,10 @@
 #define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
 #define R_USB_RH_PORT_STATUS_1__reset__no 0
 #define R_USB_RH_PORT_STATUS_1__reset__yes 1
-#define R_USB_RH_PORT_STATUS_1__overcurent__BITNR 3
-#define R_USB_RH_PORT_STATUS_1__overcurent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__overcurent__no 0
-#define R_USB_RH_PORT_STATUS_1__overcurent__yes 1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
 #define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
 #define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
 #define R_USB_RH_PORT_STATUS_1__suspended__no 0
@@ -6259,10 +6535,10 @@
 #define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
 #define R_USB_RH_PORT_STATUS_2__reset__no 0
 #define R_USB_RH_PORT_STATUS_2__reset__yes 1
-#define R_USB_RH_PORT_STATUS_2__overcurent__BITNR 3
-#define R_USB_RH_PORT_STATUS_2__overcurent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__overcurent__no 0
-#define R_USB_RH_PORT_STATUS_2__overcurent__yes 1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
 #define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
 #define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
 #define R_USB_RH_PORT_STATUS_2__suspended__no 0
@@ -6308,7 +6584,7 @@
 #define R_USB_EPT_DATA__error_code__no_error 0
 #define R_USB_EPT_DATA__error_code__stall 1
 #define R_USB_EPT_DATA__error_code__bus_error 2
-#define R_USB_EPT_DATA__error_code__TBD3 3
+#define R_USB_EPT_DATA__error_code__buffer_error 3
 #define R_USB_EPT_DATA__t_out__BITNR 21
 #define R_USB_EPT_DATA__t_out__WIDTH 1
 #define R_USB_EPT_DATA__error_count_out__BITNR 19
@@ -6357,10 +6633,10 @@
 #define R_USB_EPT_DATA_DEV__stall__WIDTH 1
 #define R_USB_EPT_DATA_DEV__stall__no 0
 #define R_USB_EPT_DATA_DEV__stall__yes 1
-#define R_USB_EPT_DATA_DEV__quiet__BITNR 28
-#define R_USB_EPT_DATA_DEV__quiet__WIDTH 1
-#define R_USB_EPT_DATA_DEV__quiet__no 0
-#define R_USB_EPT_DATA_DEV__quiet__yes 1
+#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
+#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
+#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
+#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
 #define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
 #define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
 #define R_USB_EPT_DATA_DEV__ctrl__no 0
@@ -6371,6 +6647,8 @@
 #define R_USB_EPT_DATA_DEV__iso__yes 1
 #define R_USB_EPT_DATA_DEV__port__BITNR 24
 #define R_USB_EPT_DATA_DEV__port__WIDTH 2
+#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
+#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
 #define R_USB_EPT_DATA_DEV__t__BITNR 21
 #define R_USB_EPT_DATA_DEV__t__WIDTH 1
 #define R_USB_EPT_DATA_DEV__max_len__BITNR 11
@@ -6384,6 +6662,22 @@
 #define R_USB_SNMP_TERROR__value__BITNR 0
 #define R_USB_SNMP_TERROR__value__WIDTH 32
 
+#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
+#define R_USB_EPID_ATTN__value__BITNR 0
+#define R_USB_EPID_ATTN__value__WIDTH 32
+
+#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
+#define R_USB_PORT1_DISABLE__disable__BITNR 0
+#define R_USB_PORT1_DISABLE__disable__WIDTH 1
+#define R_USB_PORT1_DISABLE__disable__yes 0
+#define R_USB_PORT1_DISABLE__disable__no 1
+
+#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
+#define R_USB_PORT2_DISABLE__disable__BITNR 0
+#define R_USB_PORT2_DISABLE__disable__WIDTH 1
+#define R_USB_PORT2_DISABLE__disable__yes 0
+#define R_USB_PORT2_DISABLE__disable__no 1
+
 /*
 !* MMU registers
 !*/
@@ -6615,6 +6909,10 @@
 #define R_MMU_CAUSE__we_excp__WIDTH 1
 #define R_MMU_CAUSE__we_excp__yes 1
 #define R_MMU_CAUSE__we_excp__no 0
+#define R_MMU_CAUSE__wr_rd__BITNR 8
+#define R_MMU_CAUSE__wr_rd__WIDTH 1
+#define R_MMU_CAUSE__wr_rd__write 1
+#define R_MMU_CAUSE__wr_rd__read 0
 #define R_MMU_CAUSE__page_id__BITNR 0
 #define R_MMU_CAUSE__page_id__WIDTH 6
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)