patch-2.4.6 linux/drivers/net/acenic.c

• Lines: 156
• Date: Thu Jun 28 14:47:10 2001
• Orig file: v2.4.5/linux/drivers/net/acenic.c
• Orig date: Fri Apr 13 20:26:07 2001

diff -u --recursive --new-file v2.4.5/linux/drivers/net/acenic.c linux/drivers/net/acenic.c
@@ -157,6 +157,9 @@
 #define __devinit	__init
 #endif
 
+#ifndef min
+#define min(a,b)	(((a)<(b))?(a):(b))
+#endif
 
 #ifndef SMP_CACHE_BYTES
 #define SMP_CACHE_BYTES	L1_CACHE_BYTES
@@ -260,6 +263,11 @@
 #define ace_if_down(dev)			{do{} while(0);}
 #endif
 
+#ifndef pci_set_dma_mask
+#define pci_set_dma_mask(dev, mask)		dev->dma_mask = mask;
+#endif
+
+
 #if (LINUX_VERSION_CODE >= 0x02031b)
 #define NEW_NETINIT
 #define ACE_PROBE_ARG				void
@@ -510,7 +518,7 @@
 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
 
 static char version[] __initdata = 
-  "acenic.c: v0.80 03/08/2001  Jes Sorensen, linux-acenic@SunSITE.dk\n"
+  "acenic.c: v0.81 04/20/2001  Jes Sorensen, linux-acenic@SunSITE.dk\n"
   "                            http://home.cern.ch/~jes/gige/acenic.html\n";
 
 static struct net_device *root_dev;
@@ -741,7 +749,7 @@
 
 
 #ifdef MODULE
-MODULE_AUTHOR("Jes Sorensen <jes@linuxcare.com>");
+MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
 MODULE_PARM(link, "1-" __MODULE_STRING(8) "i");
 MODULE_PARM(trace, "1-" __MODULE_STRING(8) "i");
@@ -1036,7 +1044,7 @@
 	u32 tig_ver, mac1, mac2, tmp, pci_state;
 	int board_idx, ecode = 0;
 	short i;
-	unsigned char cache;
+	unsigned char cache_size;
 
 	ap = dev->priv;
 	regs = ap->regs;
@@ -1169,13 +1177,18 @@
 	 * Ie. having two NICs in the machine, one will have the cache
 	 * line set at boot time, the other will not.
 	 */
-	pci_read_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE, &cache);
-	if ((cache << 2) != SMP_CACHE_BYTES) {
+	pci_read_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE, &cache_size);
+	cache_size <<= 2;
+	if (cache_size != SMP_CACHE_BYTES) {
 		printk(KERN_INFO "  PCI cache line size set incorrectly "
-		       "(%i bytes) by BIOS/FW, correcting to %i\n",
-		       (cache << 2), SMP_CACHE_BYTES);
-		pci_write_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE,
-				      SMP_CACHE_BYTES >> 2);
+		       "(%i bytes) by BIOS/FW, ", cache_size);
+		if (cache_size > SMP_CACHE_BYTES)
+			printk("expecting %i\n", SMP_CACHE_BYTES);
+		else {
+			printk("correcting to %i\n", SMP_CACHE_BYTES);
+			pci_write_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE,
+					      SMP_CACHE_BYTES >> 2);
+		}
 	}
 
 	pci_state = readl(&regs->PciState);
@@ -1186,6 +1199,12 @@
 		ap->pci_latency);
 
 	/*
+	 * Make sure to enable the 64 bit DMA mask if we're in a 64bit slot
+	 */
+	if (!(pci_state & PCI_32BIT))
+		pci_set_dma_mask(ap->pdev, (dma_addr_t)~0ULL);
+
+	/*
 	 * Set the max DMA transfer size. Seems that for most systems
 	 * the performance is better when no MAX parameter is
 	 * set. However for systems enabling PCI write and invalidate,
@@ -1210,21 +1229,10 @@
 				printk(KERN_INFO "  Disabling PCI memory "
 				       "write and invalidate\n");
 			}
-#ifdef __alpha__
-			/* This maximizes throughput on my alpha. */
-			tmp |= DMA_WRITE_MAX_128;
-#endif
 		} else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
 			printk(KERN_INFO "  PCI memory write & invalidate "
 			       "enabled by BIOS, enabling counter measures\n");
 
-#ifdef __alpha__
-			/* All the docs sy MUST NOT. Well, I did.
-			 * Nothing terrible happens, if we load wrong size.
-			 * Bit w&i still works better!
-			 */
-			tmp |= DMA_WRITE_MAX_128;
-#else
 			switch(SMP_CACHE_BYTES) {
 			case 16:
 				tmp |= DMA_WRITE_MAX_16;
@@ -1235,6 +1243,9 @@
 			case 64:
 				tmp |= DMA_WRITE_MAX_64;
 				break;
+			case 128:
+				tmp |= DMA_WRITE_MAX_128;
+				break;
 			default:
 				printk(KERN_INFO "  Cache line size %i not "
 				       "supported, PCI write and invalidate "
@@ -1243,7 +1254,6 @@
 				pci_write_config_word(ap->pdev, PCI_COMMAND,
 						      ap->pci_command);
 			}
-#endif
 		}
 	}
 
@@ -1259,12 +1269,19 @@
 	 * set will give the PCI controller proper hints about
 	 * prefetching.
 	 */
-	tmp = tmp & ~DMA_READ_WRITE_MASK;
+	tmp &= ~DMA_READ_WRITE_MASK;
 	tmp |= DMA_READ_MAX_64;
 	tmp |= DMA_WRITE_MAX_64;
 #endif
 #ifdef __alpha__
+	tmp &= ~DMA_READ_WRITE_MASK;
 	tmp |= DMA_READ_MAX_128;
+	/*
+	 * All the docs sy MUST NOT. Well, I did.
+	 * Nothing terrible happens, if we load wrong size.
+	 * Bit w&i still works better!
+	 */
+	tmp |= DMA_WRITE_MAX_128;
 #endif
 	writel(tmp, &regs->PciState);
 
@@ -3318,6 +3335,6 @@
 
 /*
  * Local variables:
- * compile-command: "gcc -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h   -c -o acenic.o acenic.c"
+ * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h   -c -o acenic.o acenic.c"
  * End:
  */