patch-2.4.4 linux/include/asm-arm/arch-ebsa110/hardware.h

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diff -u --recursive --new-file v2.4.3/linux/include/asm-arm/arch-ebsa110/hardware.h linux/include/asm-arm/arch-ebsa110/hardware.h
@@ -12,41 +12,55 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#ifndef __ASSEMBLY__
-
 /*
- * IO definitions
+ * The EBSA110 has a weird "ISA IO" region:
+ *
+ * Region 0 (addr = 0xf0000000 + io << 2)
+ * --------------------------------------------------------
+ * Physical region	IO region
+ * f0000fe0 - f0000ffc	3f8 - 3ff  ttyS0
+ * f0000e60 - f0000e64	398 - 399
+ * f0000de0 - f0000dfc	378 - 37f  lp0
+ * f0000be0 - f0000bfc	2f8 - 2ff  ttyS1
+ *
+ * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
+ * --------------------------------------------------------
+ * Physical region	IO region
+ * f00014f1             a79        pnp write data
+ * f00007c0 - f00007c1	3e0 - 3e1  pcmcia
+ * f00004f1		279        pnp address
+ * f0000440 - f000046c  220 - 236  eth0
+ * f0000405		203        pnp read data
  */
-#define PIT_CTRL		((volatile unsigned char *)0xf200000d)
-#define PIT_T2			((volatile unsigned char *)0xf2000009)
-#define PIT_T1			((volatile unsigned char *)0xf2000005)
-#define PIT_T0			((volatile unsigned char *)0xf2000001)
 
-/*
- * Mapping areas
- */
-#define IO_BASE			0xe0000000
+#define ISAMEM_PHYS		0xe0000000
+#define ISAMEM_SIZE		0x10000000
 
-/*
- * RAM definitions
- */
-#define FLUSH_BASE_PHYS		0x40000000
+#define ISAIO_PHYS		0xf0000000
+#define ISAIO_SIZE		PGDIR_SIZE
 
-#else	/* __ASSEMBLY__ */
+#define TRICK0_PHYS		0xf2000000
+#define TRICK1_PHYS		0xf2400000
+#define TRICK2_PHYS		0xf2800000
+#define TRICK3_PHYS		0xf2c00000
+#define TRICK4_PHYS		0xf3000000
+#define TRICK5_PHYS		0xf3400000
+#define TRICK6_PHYS		0xf3800000
+#define TRICK7_PHYS		0xf3c00000
 
-#define IO_BASE			0
+#define ISAMEM_BASE		0xe0000000
+#define ISAIO_BASE		0xf0000000
 
-#endif	/* __ASSEMBLY__ */
-
-#define IO_SIZE			0x20000000
-#define IO_START		0xe0000000
+#define PIT_BASE		0xfc000000
+#define SOFT_BASE		0xfd000000
 
+/*
+ * RAM definitions
+ */
+#define FLUSH_BASE_PHYS		0x40000000
 #define FLUSH_BASE		0xdf000000
-#define PCIO_BASE		0xf0000000
-
-#define UNCACHEABLE_ADDR	0xf3000000
 
-#define PARAMS_OFFSET		0x400
+#define UNCACHEABLE_ADDR	0xff000000	/* IRQ_STAT */
 
 #endif
 

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