patch-2.4.25 linux-2.4.25/arch/mips/mm/tlbex-r4k.S

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Lines: 287
Date: 2004-02-18 05:36:30.000000000 -0800
Orig file: linux-2.4.24/arch/mips/mm/tlbex-r4k.S
Orig date: 2003-08-25 04:44:40.000000000 -0700

diff -urN linux-2.4.24/arch/mips/mm/tlbex-r4k.S linux-2.4.25/arch/mips/mm/tlbex-r4k.S
@@ -32,21 +32,19 @@
 #define PTE_S		sd
 #define PTE_SRL		dsrl
 #define P_MTC0		dmtc0
-#define PTE_SIZE	8
-#define PTEP_INDX_MSK	0xff0
-#define PTE_INDX_MSK	0xff8
-#define PTE_INDX_SHIFT	9
 #else
 #define PTE_L		lw
 #define PTE_S		sw
 #define PTE_SRL		srl
 #define P_MTC0		mtc0
-#define PTE_SIZE	4
-#define PTEP_INDX_MSK	0xff8
-#define PTE_INDX_MSK	0xffc
-#define PTE_INDX_SHIFT	10
 #endif
 
+#define PTE_PAGE_SIZE	(_PAGE_SIZE << _PTE_ORDER)
+#define PTE_PAGE_SHIFT	(_PAGE_SHIFT + _PTE_ORDER)
+#define PTEP_INDX_MSK	((PTE_PAGE_SIZE - 1) & ~(_PTE_T_SIZE << 1 - 1))
+#define PTE_INDX_MSK	((PTE_PAGE_SIZE - 1) & ~(_PTE_T_SIZE - 1))
+#define PTE_INDX_SHIFT	(PTE_PAGE_SHIFT - _PTE_T_LOG2)
+
 /*
  * ABUSE of CPP macros 101.
  *
@@ -72,7 +70,7 @@
 	GET_PGD(pte, ptr)          \
 	mfc0	pte, CP0_BADVADDR; \
 	srl	pte, pte, _PGDIR_SHIFT; \
-	sll	pte, pte, 2; \
+	sll	pte, pte, _PGD_T_LOG2; \
 	addu	ptr, ptr, pte; \
 	mfc0	pte, CP0_BADVADDR; \
 	lw	ptr, (ptr); \
@@ -86,9 +84,9 @@
 	 * TMP as a scratch register.
 	 */
 #define PTE_RELOAD(ptr, tmp) \
-	ori	ptr, ptr, PTE_SIZE; \
-	xori	ptr, ptr, PTE_SIZE; \
-	PTE_L	tmp, PTE_SIZE(ptr); \
+	ori	ptr, ptr, _PTE_T_SIZE; \
+	xori	ptr, ptr, _PTE_T_SIZE; \
+	PTE_L	tmp, _PTE_T_SIZE(ptr); \
 	PTE_L	ptr, 0(ptr); \
 	PTE_SRL	tmp, tmp, 6; \
 	P_MTC0	tmp, CP0_ENTRYLO1; \
@@ -143,14 +141,22 @@
 
 	__INIT
 
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define GET_PTE_OFF(reg)
-#elif CONFIG_CPU_VR41XX
-#define GET_PTE_OFF(reg)	srl	reg, reg, 3
+/*
+ * Different for VR41xx because it supports 1k as smallest page size
+ */
+#ifdef CONFIG_CPU_VR41XX
+#define BASE_VPN_SHIFT	6
+#else
+#define BASE_VPN_SHIFT	4
+#endif
+
+#if (BASE_VPN_SHIFT- PTE_T_LOG2-1) > 0
+#define GET_PTE_OFF(reg)	srl	reg, reg, BASE_VPN_SHIFT-_PTE_T_LOG2-1
 #else
-#define GET_PTE_OFF(reg)	srl	reg, reg, 1
+#define GET_PTE_OFF(reg)
 #endif
 
+
 /*
  * These handlers much be written in a relocatable manner
  * because based upon the cpu type an arbitrary one of the
@@ -165,8 +171,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR		# Get faulting address
 	srl	k0, k0, _PGDIR_SHIFT		# get pgd only bits
-
-	sll	k0, k0, 2
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0			# add in pgd offset
 	mfc0	k0, CP0_CONTEXT			# get context reg
 	lw	k1, (k1)
@@ -174,15 +179,17 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0			# add in offset
 	PTE_L	k0, 0(k1)			# get even pte
-	PTE_L	k1, PTE_SIZE(k1)		# get odd pte
+	PTE_L	k1, _PTE_T_SIZE(k1)		# get odd pte
 	PTE_SRL	k0, k0, 6			# convert to entrylo0
 	P_MTC0	k0, CP0_ENTRYLO0		# load it
 	PTE_SRL	k1, k1, 6			# convert to entrylo1
 	P_MTC0	k1, CP0_ENTRYLO1		# load it
 	b	1f
+	rm9000_tlb_hazard
 	tlbwr					# write random tlb entry
 1:
 	nop
+	rm9000_tlb_hazard
 	eret					# return from trap
 	END(except_vec0_r4000)
 
@@ -192,7 +199,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR
 	srl	k0, k0, _PGDIR_SHIFT
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0
 	mfc0	k0, CP0_CONTEXT
 	lw	k1, (k1)
@@ -200,7 +207,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0
 	PTE_L	k0, 0(k1)
-	PTE_L	k1, PTE_SIZE(k1)
+	PTE_L	k1, _PTE_T_SIZE(k1)
 	PTE_SRL	k0, k0, 6
 	P_MTC0	k0, CP0_ENTRYLO0
 	PTE_SRL	k1, k1, 6
@@ -228,7 +235,7 @@
 	mfc0	k0, CP0_BADVADDR		# Get faulting address
 	srl	k0, k0, _PGDIR_SHIFT		# get pgd only bits
 	lw	k1, pgd_current			# get pgd pointer
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0			# add in pgd offset
 	lw	k1, (k1)
 	mfc0	k0, CP0_CONTEXT			# get context reg
@@ -236,7 +243,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0			# add in offset
 	PTE_L	k0, 0(k1)			# get even pte
-	PTE_L	k1, PTE_SIZE(k1)		# get odd pte
+	PTE_L	k1, _PTE_T_SIZE(k1)		# get odd pte
 	PTE_SRL	k0, k0, 6			# convert to entrylo0
 	P_MTC0	k0, CP0_ENTRYLO0		# load it
 	PTE_SRL	k1, k1, 6			# convert to entrylo1
@@ -260,7 +267,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR		# Get faulting address
 	srl	k0, k0, _PGDIR_SHIFT		# get pgd only bits
-	sll	k0, k0, 2
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0			# add in pgd offset
 	mfc0	k0, CP0_CONTEXT			# get context reg
 	lw	k1, (k1)
@@ -268,7 +275,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0			# add in offset
 	PTE_L	k0, 0(k1)			# get even pte
-	PTE_L	k1, PTE_SIZE(k1)		# get odd pte
+	PTE_L	k1, _PTE_T_SIZE(k1)		# get odd pte
 	PTE_SRL	k0, k0, 6			# convert to entrylo0
 	P_MTC0	k0, CP0_ENTRYLO0		# load it
 	PTE_SRL	k1, k1, 6			# convert to entrylo1
@@ -283,7 +290,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR
 	srl	k0, k0, _PGDIR_SHIFT
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0
 	mfc0	k0, CP0_CONTEXT
 	lw	k1, (k1)
@@ -293,7 +300,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0
 	PTE_L	k0, 0(k1)
-	PTE_L	k1, PTE_SIZE(k1)
+	PTE_L	k1, _PTE_T_SIZE(k1)
 	nop				/* XXX */
 	tlbp
 	PTE_SRL	k0, k0, 6
@@ -315,7 +322,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR
 	srl	k0, k0, _PGDIR_SHIFT
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0
 	mfc0	k0, CP0_CONTEXT
 	lw	k1, (k1)
@@ -325,7 +332,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0
 	PTE_L	k0, 0(k1)
-	PTE_L	k1, PTE_SIZE(k1)
+	PTE_L	k1, _PTE_T_SIZE(k1)
 	nop				/* XXX */
 	tlbp
 	PTE_SRL	k0, k0, 6
@@ -347,7 +354,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR
 	srl	k0, k0, _PGDIR_SHIFT
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0
 	mfc0	k0, CP0_CONTEXT
 	lw	k1, (k1)
@@ -357,7 +364,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0
 	PTE_L	k0, 0(k1)
-	PTE_L	k1, PTE_SIZE(k1)
+	PTE_L	k1, _PTE_T_SIZE(k1)
 	PTE_SRL	k0, k0, 6
 	P_MTC0	zero, CP0_ENTRYLO0
 	P_MTC0	k0, CP0_ENTRYLO0
@@ -378,7 +385,7 @@
 	GET_PGD(k0, k1)				# get pgd pointer
 	mfc0	k0, CP0_BADVADDR
 	srl	k0, k0, _PGDIR_SHIFT
-	sll	k0, k0, 2			# log2(sizeof(pgd_t)
+	sll	k0, k0, _PGD_T_LOG2
 	addu	k1, k1, k0
 	mfc0	k0, CP0_CONTEXT
 	lw	k1, (k1)
@@ -388,7 +395,7 @@
 	and	k0, k0, PTEP_INDX_MSK
 	addu	k1, k1, k0
 	PTE_L	k0, 0(k1)
-	PTE_L	k1, PTE_SIZE(k1)
+	PTE_L	k1, _PTE_T_SIZE(k1)
 	nop				/* XXX */
 	tlbp
 	PTE_SRL	k0, k0, 6
@@ -453,6 +460,7 @@
 #endif
 invalid_tlbl:
 #ifdef TLB_OPTIMIZE
+	.set	mips3
 	/* Test present bit in entry. */
 	LOAD_PTE(k0, k1)
 	R5K_HAZARD
@@ -460,11 +468,13 @@
 	PTE_PRESENT(k0, k1, nopage_tlbl)
 	PTE_MAKEVALID(k0, k1)
 	PTE_RELOAD(k1, k0)
+	rm9000_tlb_hazard
 	nop
 	b	1f
 	 tlbwi
 1:
 	nop
+	rm9000_tlb_hazard
 	.set	mips3
 	eret
 	.set	mips0
@@ -486,11 +496,13 @@
 	PTE_WRITABLE(k0, k1, nopage_tlbs)
 	PTE_MAKEWRITE(k0, k1)
 	PTE_RELOAD(k1, k0)
+	rm9000_tlb_hazard
 	nop
 	b	1f
 	 tlbwi
 1:
 	nop
+	rm9000_tlb_hazard
 	.set	mips3
 	eret
 	.set	mips0
@@ -517,10 +529,12 @@
 
 	/* Now reload the entry into the tlb. */
 	PTE_RELOAD(k1, k0)
+	rm9000_tlb_hazard
 	nop
 	b	1f
 	 tlbwi
 1:
+	rm9000_tlb_hazard
 	nop
 	.set	mips3
 	eret
@@ -530,4 +544,3 @@
 nowrite_mod:
 	DO_FAULT(1)
 	END(handle_mod)
-
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