patch-2.4.23 linux-2.4.23/include/asm-ppc/mmu.h

• Lines: 74
• Date: 2003-11-28 10:26:21.000000000 -0800
• Orig file: linux-2.4.22/include/asm-ppc/mmu.h
• Orig date: 2003-08-25 04:44:44.000000000 -0700

diff -urN linux-2.4.22/include/asm-ppc/mmu.h linux-2.4.23/include/asm-ppc/mmu.h
@@ -10,6 +10,18 @@
 
 #ifndef __ASSEMBLY__
 
+/*
+ * Define physical address type.  Machines using split size
+ * virtual/physical addressing like 32-bit virtual / 36-bit
+ * physical need a larger than native word size type. -Matt
+ */
+#ifdef CONFIG_PTE_64BIT
+typedef unsigned long long phys_addr_t;
+extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+#else
+typedef unsigned long phys_addr_t;
+#endif
+
 /* Default "unsigned long" context */
 typedef unsigned long mm_context_t;
 
@@ -326,5 +338,54 @@
 #define TLB_M           0x00000002      /* Memory is coherent */
 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
 
+/*
+ * PPC44x support
+ */
+#define PPC44x_MMUCR_TID	0x000000ff	
+#define PPC44x_MMUCR_STS	0x00010000
+
+#define	PPC44x_TLB_PAGEID	0
+#define	PPC44x_TLB_XLAT		1
+#define	PPC44x_TLB_ATTRIB	2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK	0xfffffc00      /* Effective Page Number */
+#define	PPC44x_TLB_VALID	0x00000200      /* Valid flag */
+#define PPC44x_TLB_TS		0x00000100	/* Translation address space */
+#define PPC44x_TLB_PAGESZ_MASK	0x000000f0
+#define PPC44x_TLB_PAGESZ(x)	(x << 4)
+#define PPC44x_PAGESZ_1K	0
+#define PPC44x_PAGESZ_4K	1
+#define PPC44x_PAGESZ_16K	2
+#define PPC44x_PAGESZ_64K	3
+#define PPC44x_PAGESZ_256K	4
+#define PPC44x_PAGESZ_1M	5
+#define PPC44x_PAGESZ_16M	7
+#define	PPC44x_PAGESZ_256M	9
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK	0xfffffc00      /* Real Page Number */
+#define	PPC44x_TLB_ERPN_MASK	0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK	0x0000ff80
+#define PPC44x_TLB_U0		0x00008000      /* User 0 */
+#define PPC44x_TLB_U1		0x00004000      /* User 1 */
+#define PPC44x_TLB_U2		0x00002000      /* User 2 */
+#define PPC44x_TLB_U3		0x00001000      /* User 3 */
+#define PPC44x_TLB_W		0x00000800      /* Caching is write-through */
+#define PPC44x_TLB_I		0x00000400      /* Caching is inhibited */
+#define PPC44x_TLB_M		0x00000200      /* Memory is coherent */
+#define PPC44x_TLB_G		0x00000100      /* Memory is guarded */
+#define PPC44x_TLB_E		0x00000080      /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK	0x0000003f
+#define PPC44x_TLB_UX		0x00000020      /* User execution */
+#define PPC44x_TLB_UW		0x00000010      /* User write */
+#define PPC44x_TLB_UR		0x00000008      /* User read */
+#define PPC44x_TLB_SX		0x00000004      /* Super execution */
+#define PPC44x_TLB_SW		0x00000002      /* Super write */
+#define PPC44x_TLB_SR		0x00000001      /* Super read */
+
 #endif /* _PPC_MMU_H_ */
 #endif /* __KERNEL__ */