patch-2.4.22 linux-2.4.22/include/asm-mips/vr41xx/eagle.h

• Lines: 143
• Date: 2003-08-25 04:44:44.000000000 -0700
• Orig file: linux-2.4.21/include/asm-mips/vr41xx/eagle.h
• Orig date: 2002-11-28 15:53:15.000000000 -0800

diff -urN linux-2.4.21/include/asm-mips/vr41xx/eagle.h linux-2.4.22/include/asm-mips/vr41xx/eagle.h
@@ -8,7 +8,7 @@
  * Author: MontaVista Software, Inc.
  *         yyuasa@mvista.com or source@mvista.com
  *
- * Copyright 2001,2002 MontaVista Software Inc.
+ * Copyright 2001-2003 MontaVista Software Inc.
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License as published by the
@@ -81,23 +81,25 @@
 #define FPGA_CASCADE_IRQ		GIU_IRQ(FPGA_PIN)
 #define DCD_IRQ				GIU_IRQ(DCD_PIN)
 
-#define SDBINT_IRQ_BASE			89
-#define DEG_IRQ				(SDBINT_IRQ_BASE + 1)
-#define ENUM_IRQ			(SDBINT_IRQ_BASE + 2)
-#define SIO1INT_IRQ			(SDBINT_IRQ_BASE + 3)
-#define SIO2INT_IRQ			(SDBINT_IRQ_BASE + 4)
-#define PARINT_IRQ			(SDBINT_IRQ_BASE + 5)
+#define SDBINT_IRQ_BASE			88
+#define SDBINT_IRQ(x)			(SDBINT_IRQ_BASE + (x))
+/* RFU */
+#define DEG_IRQ				SDBINT_IRQ(1)
+#define ENUM_IRQ			SDBINT_IRQ(2)
+#define SIO1INT_IRQ			SDBINT_IRQ(3)
+#define SIO2INT_IRQ			SDBINT_IRQ(4)
+#define PARINT_IRQ			SDBINT_IRQ(5)
 #define SDBINT_IRQ_LAST			PARINT_IRQ
 
-#define PCIINT_IRQ_BASE			97
-#define CP_INTA_IRQ			(PCIINT_IRQ_BASE + 0)
-#define CP_INTB_IRQ			(PCIINT_IRQ_BASE + 1)
-#define CP_INTC_IRQ			(PCIINT_IRQ_BASE + 2)
-#define CP_INTD_IRQ			(PCIINT_IRQ_BASE + 3)
-#define LANINTA_IRQ			(PCIINT_IRQ_BASE + 4)
+#define PCIINT_IRQ_BASE			96
+#define PCIINT_IRQ(x)			(PCIINT_IRQ_BASE + (x))
+#define CP_INTA_IRQ			PCIINT_IRQ(0)
+#define CP_INTB_IRQ			PCIINT_IRQ(1)
+#define CP_INTC_IRQ			PCIINT_IRQ(2)
+#define CP_INTD_IRQ			PCIINT_IRQ(3)
+#define LANINTA_IRQ			PCIINT_IRQ(4)
 #define PCIINT_IRQ_LAST			LANINTA_IRQ
 
-
 /*
  * On board Devices I/O Mapping
  */
@@ -134,7 +136,6 @@
 #define NEC_EAGLE_PIOECP_CONFIG		KSEG1ADDR(0x0DFFFEF2)
 #define NEC_EAGLE_PIOECP_EXTCNT		KSEG1ADDR(0x0DFFFEF4)
 
-
 /*
  *  FLSHCNT Register
  */
@@ -143,7 +144,6 @@
 #define NEC_EAGLE_FLSHCNT_VPPE		0x40
 #define NEC_EAGLE_FLSHCNT_WP2		0x01
 
-
 /*
  * FLSHBANK Register
  */
@@ -156,7 +156,6 @@
 #define NEC_EAGLE_FLSHBANK_BNKQ1	0x02
 #define NEC_EAGLE_FLSHBANK_BNKQ0	0x01
 
-
 /*
  * SWITCH Setting Register
  */
@@ -170,7 +169,6 @@
 #define NEC_EAGLE_SWTCHSET_DP1SW2	0x02
 #define NEC_EAGLE_SWTCHSET_DP1SW1	0x01
 
-
 /*
  * PPT Parallel Port Device Controller
  */
@@ -196,14 +194,12 @@
 #define NEC_EAGLE_PPT_SELECT		0x02
 #define NEC_EAGLE_PPT_FAULT		0x01
 
-
 /*
  * LEDWR Register
  */
 #define NEC_EAGLE_LEDWR1		KSEG1ADDR(0x0DFFFFC0)
 #define NEC_EAGLE_LEDWR2		KSEG1ADDR(0x0DFFFFC4)
 
-
 /*
  * SDBINT Register
  */
@@ -214,7 +210,6 @@
 #define NEC_EAGLE_SDBINT_ENUM		0x04
 #define NEC_EAGLE_SDBINT_DEG		0x02
 
-
 /*
  * SDB INTMSK Register
  */
@@ -225,7 +220,6 @@
 #define NEC_EAGLE_SDBINTMSK_MSKENUM	0x04
 #define NEC_EAGLE_SDBINTMSK_MSKDEG	0x02
 
-
 /*
  * RSTREG Register
  */
@@ -233,7 +227,6 @@
 #define NEC_EAGLE_RST_RSTSW		0x02
 #define NEC_EAGLE_RST_LEDOFF		0x01
 
-
 /*
  * PCI INT Rgister
  */
@@ -244,7 +237,6 @@
 #define NEC_EAGLE_PCIINT_CP_INTB	0x02
 #define NEC_EAGLE_PCIINT_CP_INTA	0x01
 
-
 /*
  * PCI INT Mask Register
  */
@@ -255,7 +247,6 @@
 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTB	0x02
 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTA	0x01
 
-
 /*
  * CLK Division Register
  */
@@ -266,7 +257,6 @@
 #define NEC_EAGLE_CLKDIV_VTDIV1		0x02
 #define NEC_EAGLE_CLKDIV_VTDIV0		0x01
 
-
 /*
  * Source Revision Register
  */