patch-2.4.22 linux-2.4.22/include/asm-arm/arch-epxa/exc-epxa1db.h

• Lines: 84
• Date: 2003-08-25 04:44:43.000000000 -0700
• Orig file: linux-2.4.21/include/asm-arm/arch-epxa/exc-epxa1db.h
• Orig date: 1969-12-31 16:00:00.000000000 -0800

diff -urN linux-2.4.21/include/asm-arm/arch-epxa/exc-epxa1db.h linux-2.4.22/include/asm-arm/arch-epxa/exc-epxa1db.h
@@ -0,0 +1,83 @@
+/* megafunction wizard: %ARM-Based Excalibur%
+   GENERATION: STANDARD
+   VERSION: WM1.0
+   MODULE: ARM-Based Excalibur
+   PROJECT: excalibur
+   ============================================================
+   File Name: D:\tmp\quartus\excalibur.h
+   Megafunction Name(s): ARM-Based Excalibur
+   ============================================================
+
+   ************************************************************
+   THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+   ************************************************************/
+
+#ifndef	EXCALIBUR_H_INCLUDED
+#define	EXCALIBUR_H_INCLUDED
+
+#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
+#define EXC_DEFINE_BOOT_FROM_FLASH
+
+#define	EXC_INPUT_CLK_FREQUENCY (25000000)
+#define	EXC_AHB1_CLK_FREQUENCY (200000000)
+#define	EXC_AHB2_CLK_FREQUENCY (100000000)
+#define	EXC_SDRAM_CLK_FREQUENCY (35341652)
+
+/* Registers Block */
+#define	EXC_REGISTERS_BASE (0x7fffc000)
+#define	EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
+#define	EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
+#define	EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
+#define	EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
+#define	EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
+#define	EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
+#define	EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
+#define	EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
+#define	EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
+#define	EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
+#define	EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
+#define	EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
+#define	EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+#define	EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+
+#define	EXC_REGISTERS_SIZE (0x00004000)
+
+/* EBI Block(s) */
+#define	EXC_EBI_BLOCK0_BASE (0x40000000)
+#define	EXC_EBI_BLOCK0_SIZE (0x00400000)
+#define	EXC_EBI_BLOCK0_WIDTH (16)
+#define	EXC_EBI_BLOCK0_NON_CACHEABLE
+#define	EXC_EBI_BLOCK1_BASE (0x40400000)
+#define	EXC_EBI_BLOCK1_SIZE (0x00400000)
+#define	EXC_EBI_BLOCK1_WIDTH (16)
+#define	EXC_EBI_BLOCK1_NON_CACHEABLE
+#define	EXC_EBI_BLOCK3_BASE (0x40c00000)
+#define	EXC_EBI_BLOCK3_SIZE (0x00400000)
+#define	EXC_EBI_BLOCK3_WIDTH (16)
+#define	EXC_EBI_BLOCK3_NON_CACHEABLE
+
+/* SDRAM Block(s) */
+#define	EXC_SDRAM_BLOCK0_BASE (0x00000000)
+#define	EXC_SDRAM_BLOCK0_SIZE (0x02000000)
+#define	EXC_SDRAM_BLOCK0_WIDTH (16)
+
+/* Single Port SRAM Block(s) */
+#define	EXC_SPSRAM_BLOCK0_BASE (0x20000000)
+#define	EXC_SPSRAM_BLOCK0_SIZE (0x00004000)
+#define	EXC_SPSRAM_BLOCK1_BASE (0x20020000)
+#define	EXC_SPSRAM_BLOCK1_SIZE (0x00004000)
+
+/* Dual Port SRAM Block(s) */
+#define	EXC_DPSRAM_BLOCK0_BASE (0x20040000)
+#define	EXC_DPSRAM_BLOCK0_SIZE (0x00004000)
+#define	EXC_DPSRAM_BLOCK0_WIDTH (0)
+
+/* PLD Block(s) */
+#define	EXC_PLD_BLOCK0_BASE (0x80000000)
+#define	EXC_PLD_BLOCK0_SIZE (0x80000000)
+#define	EXC_PLD_BLOCK0_NON_CACHEABLE
+#define	EXC_PLD_BLOCK1_BASE (0x60000000)
+#define	EXC_PLD_BLOCK1_SIZE (0x10000000)
+#define	EXC_PLD_BLOCK1_NON_CACHEABLE
+
+#endif