patch-2.4.20 linux-2.4.20/include/asm-mips/war.h

• Lines: 43
• Date: Thu Nov 28 15:53:15 2002
• Orig file: linux-2.4.19/include/asm-mips/war.h
• Orig date: Fri Aug 2 17:39:45 2002

diff -urN linux-2.4.19/include/asm-mips/war.h linux-2.4.20/include/asm-mips/war.h
@@ -8,6 +8,8 @@
 #ifndef _ASM_WAR_H
 #define _ASM_WAR_H
 
+#include <linux/config.h>
+
 /*
  * Pleassures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
  *
@@ -15,10 +17,10 @@
  *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
  *      executed if there is no other dcache activity. If the dcache is
  *      accessed for another instruction immeidately preceding when these
- *      cache instructions are executing, it is possible that the dcache 
- *      tag match outputs used by these cache instructions will be 
+ *      cache instructions are executing, it is possible that the dcache
+ *      tag match outputs used by these cache instructions will be
  *      incorrect. These cache instructions should be preceded by at least
- *      four instructions that are not any kind of load or store 
+ *      four instructions that are not any kind of load or store
  *      instruction.
  *
  *      This is not allowed:    lw
@@ -50,4 +52,19 @@
  */
 #define R4600_V2_HIT_CACHEOP_WAR
 
+#ifdef CONFIG_CPU_R5432
+
+/*
+ * When an interrupt happens on a CP0 register read instruction, CPU may
+ * lock up or read corrupted values of CP0 registers after it enters
+ * the exception handler.
+ *
+ * This workaround makes sure that we read a "safe" CP0 register as the
+ * first thing in the exception handler, which breaks one of the
+ * pre-conditions for this problem.
+ */
+#define	R5432_CP0_INTERRUPT_WAR
+
+#endif
+
 #endif /* _ASM_WAR_H */