patch-2.4.20 linux-2.4.20/arch/mips/math-emu/cp1emu.c
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- Lines: 1862
- Date:
Thu Nov 28 15:53:10 2002
- Orig file:
linux-2.4.19/arch/mips/math-emu/cp1emu.c
- Orig date:
Fri Aug 2 17:39:43 2002
diff -urN linux-2.4.19/arch/mips/math-emu/cp1emu.c linux-2.4.20/arch/mips/math-emu/cp1emu.c
@@ -1,6 +1,6 @@
/*
* cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
- *
+ *
* MIPS floating point support
* Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved.
* http://www.algor.co.uk
@@ -23,38 +23,30 @@
*
* A complete emulator for MIPS coprocessor 1 instructions. This is
* required for #float(switch) or #float(trap), where it catches all
- * COP1 instructions via the "CoProcessor Unusable" exception.
+ * COP1 instructions via the "CoProcessor Unusable" exception.
*
* More surprisingly it is also required for #float(ieee), to help out
* the hardware fpu at the boundaries of the IEEE-754 representation
* (denormalised values, infinities, underflow, etc). It is made
* quite nasty because emulation of some non-COP1 instructions is
* required, e.g. in branch delay slots.
- *
- * Note if you know that you won't have an fpu, then you'll get much
+ *
+ * Note if you know that you won't have an fpu, then you'll get much
* better performance by compiling with -msoft-float!
*/
-#include <linux/compiler.h>
-#include <linux/mm.h>
-#include <linux/signal.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-
-#include <asm/asm.h>
-#include <asm/branch.h>
+#include <asm/inst.h>
#include <asm/bootinfo.h>
-#include <asm/byteorder.h>
#include <asm/cpu.h>
-#include <asm/inst.h>
-#include <asm/uaccess.h>
#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/signal.h>
#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-
#include <asm/fpu_emulator.h>
+#include <asm/uaccess.h>
+#include <asm/branch.h>
#include "ieee754.h"
+#include "dsemul.h"
/* Strap kernel emulator for full MIPS IV emulation */
@@ -63,20 +55,14 @@
#endif
#define __mips 4
-typedef void *vaddr_t;
-
-/* Function which emulates the instruction in a branch delay slot. */
-
-static int mips_dsemul(struct pt_regs *, mips_instruction, unsigned long);
-
/* Function which emulates a floating point instruction. */
static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *,
- mips_instruction);
+ mips_instruction);
#if __mips >= 4 && __mips != 32
static int fpux_emu(struct pt_regs *,
- struct mips_fpu_soft_struct *, mips_instruction);
+ struct mips_fpu_soft_struct *, mips_instruction);
#endif
/* Further private data for which no space exists in mips_fpu_soft_struct */
@@ -108,8 +94,7 @@
#endif
-
-/*
+/*
* Redundant with logic already in kernel/branch.c,
* embedded in compute_return_epc. At some point,
* a single subroutine should be used across both
@@ -165,46 +150,70 @@
return 0;
}
-#define REG_TO_VA (vaddr_t)
-#define VA_TO_REG (unsigned long)
-
/*
* In the Linux kernel, we support selection of FPR format on the
* basis of the Status.FR bit. This does imply that, if a full 32
* FPRs are desired, there needs to be a flip-flop that can be written
- * to one at that bit position. In any case, normal MIPS ABI uses
+ * to one at that bit position. In any case, O32 MIPS ABI uses
* only the even FPRs (Status.FR = 0).
*/
#define CP0_STATUS_FR_SUPPORT
+#ifdef CP0_STATUS_FR_SUPPORT
+#define FR_BIT ST0_FR
+#else
+#define FR_BIT 0
+#endif
+
+#define SIFROMREG(si,x) ((si) = \
+ (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
+ (int)ctx->regs[x] : \
+ (int)(ctx->regs[x & ~1] >> 32 ))
+#define SITOREG(si,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
+ (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
+ ctx->regs[x & ~1] >> 32 << 32 | (u32)(si) : \
+ ctx->regs[x & ~1] << 32 >> 32 | (u64)(si) << 32)
+
+#define DIFROMREG(di,x) ((di) = \
+ ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)])
+#define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
+ = (di))
+#define DIFROMREG(di,x) ((di) = \
+ ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)])
+#define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
+ = (di))
+
+#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
+#define SPTOREG(sp,x) SITOREG((sp).bits,x)
+#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
+#define DPTOREG(dp,x) DITOREG((dp).bits,x)
+
/*
* Emulate the single floating point instruction pointed at by EPC.
* Two instructions if the instruction is in a branch delay slot.
*/
-static int cop1Emulate(struct pt_regs *regs, struct mips_fpu_soft_struct *ctx)
+static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
{
- vaddr_t emulpc, contpc;
mips_instruction ir;
+ vaddr_t emulpc, contpc;
unsigned int cond;
- int err = 0;
- err = get_user(ir, (mips_instruction *) regs->cp0_epc);
- if (err) {
+ if (get_user(ir, (mips_instruction *) REG_TO_VA xcp->cp0_epc)) {
fpuemuprivate.stats.errors++;
return SIGBUS;
}
/* XXX NEC Vr54xx bug workaround */
- if ((regs->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
- regs->cp0_cause &= ~CAUSEF_BD;
+ if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
+ xcp->cp0_cause &= ~CAUSEF_BD;
- if (regs->cp0_cause & CAUSEF_BD) {
+ if (xcp->cp0_cause & CAUSEF_BD) {
/*
* The instruction to be emulated is in a branch delay slot
* which means that we have to emulate the branch instruction
- * BEFORE we do the cop1 instruction.
+ * BEFORE we do the cop1 instruction.
*
* This branch could be a COP1 branch, but in that case we
* would have had a trap for that instruction, and would not
@@ -213,368 +222,206 @@
* Linux MIPS branch emulator operates on context, updating the
* cp0_epc.
*/
- emulpc = REG_TO_VA(regs->cp0_epc + 4); /* Snapshot emulation target */
+ emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */
- if (__compute_return_epc(regs)) {
+ if (__compute_return_epc(xcp)) {
#ifdef CP1DBG
printk("failed to emulate branch at %p\n",
- REG_TO_VA(regs->cp0_epc));
+ REG_TO_VA(xcp->cp0_epc));
#endif
return SIGILL;
}
- err = get_user(ir, (mips_instruction *) emulpc);
- if (err) {
+ if (get_user(ir, (mips_instruction *) emulpc)) {
fpuemuprivate.stats.errors++;
return SIGBUS;
}
/* __computer_return_epc() will have updated cp0_epc */
- contpc = REG_TO_VA regs->cp0_epc;
+ contpc = REG_TO_VA xcp->cp0_epc;
/* In order not to confuse ptrace() et al, tweak context */
- regs->cp0_epc = VA_TO_REG emulpc - 4;
- } else {
- emulpc = REG_TO_VA regs->cp0_epc;
- contpc = REG_TO_VA regs->cp0_epc + 4;
+ xcp->cp0_epc = VA_TO_REG emulpc - 4;
+ }
+ else {
+ emulpc = REG_TO_VA xcp->cp0_epc;
+ contpc = REG_TO_VA(xcp->cp0_epc + 4);
}
-emul:
+ emul:
fpuemuprivate.stats.emulated++;
switch (MIPSInst_OPCODE(ir)) {
-#ifdef CP0_STATUS_FR_SUPPORT
- /* R4000+ 64-bit fpu registers */
#ifndef SINGLE_ONLY_FPU
- case ldc1_op:
- {
- u64 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- int ft = MIPSInst_RT(ir);
-
- if (!(regs->cp0_status & ST0_FR))
- ft &= ~1;
- err = get_user(ctx->regs[ft], va);
- fpuemuprivate.stats.loads++;
- if (err) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
+ case ldc1_op:{
+ u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
+ MIPSInst_SIMM(ir));
+ u64 val;
+
+ fpuemuprivate.stats.loads++;
+ if (get_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
}
+ DITOREG(val, MIPSInst_RT(ir));
break;
+ }
- case sdc1_op:
- {
- fpureg_t *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- int ft = MIPSInst_RT(ir);
-
- if (!(regs->cp0_status & ST0_FR))
- ft &= ~1;
- fpuemuprivate.stats.stores++;
- if (put_user(ctx->regs[ft], va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
+ case sdc1_op:{
+ u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
+ MIPSInst_SIMM(ir));
+ u64 val;
+
+ fpuemuprivate.stats.stores++;
+ DIFROMREG(val, MIPSInst_RT(ir));
+ if (put_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
}
break;
+ }
#endif
- case lwc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- int ft = MIPSInst_RT(ir);
- u32 val;
+ case lwc1_op:{
+ u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
+ MIPSInst_SIMM(ir));
+ u32 val;
- fpuemuprivate.stats.loads++;
- err = get_user(val, va);
- if (err) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- if (regs->cp0_status & ST0_FR) {
- /* load whole register */
- ctx->regs[ft] = (s64) val;
- } else if (ft & 1) {
- /* load to m.s. 32 bits */
-#ifdef SINGLE_ONLY_FPU
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- ctx->regs[(ft & ~1)] &= 0xffffffff;
- ctx->regs[(ft & ~1)] |= (fpureg_t) val << 32;
-#endif
- } else {
- /* load to l.s. 32 bits */
- ctx->regs[ft] &= ~0xffffffffLL;
- ctx->regs[ft] |= val;
- }
+ fpuemuprivate.stats.loads++;
+ if (get_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
}
- break;
-
- case swc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- unsigned int val;
- int ft = MIPSInst_RT(ir);
-
- fpuemuprivate.stats.stores++;
- if (regs->cp0_status & ST0_FR) {
- /* store whole register */
- val = ctx->regs[ft];
- } else if (ft & 1) {
#ifdef SINGLE_ONLY_FPU
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- /* store from m.s. 32 bits */
- val = ctx->regs[(ft & ~1)] >> 32;
-#endif
- } else {
- /* store from l.s. 32 bits */
- val = ctx->regs[ft];
- }
- if (put_user(val, va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- }
- break;
-#else /* old 32-bit fpu registers */
- case lwc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- err = get_user(ctx->regs[MIPSInst_RT(ir)], va);
-
- fpuemuprivate.stats.loads++;
- if (err) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- }
- break;
-
- case swc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- fpuemuprivate.stats.stores++;
- if (put_user(ctx->regs[MIPSInst_RT(ir)], va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
+ if (MIPSInst_RT(ir) & 1) {
+ /* illegal register in single-float mode */
+ return SIGILL;
}
- break;
- case ldc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)])
- + MIPSInst_SIMM(ir);
- unsigned int rt = MIPSInst_RT(ir) & ~1;
- int errs = 0;
- fpuemuprivate.stats.loads++;
-#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__)
- err = get_user(ctx->regs[rt + 1], va + 0);
- err |= get_user(ctx->regs[rt + 0], va + 1);
-#else
- err = get_user(ctx->regs[rt + 0], va + 0);
- err |= get_user(ctx->regs[rt + 1], va + 1);
#endif
- if (err)
- return SIGBUS;
- }
+ SITOREG(val, MIPSInst_RT(ir));
break;
+ }
- case sdc1_op:
- {
- u32 *va = REG_TO_VA(regs->regs[MIPSInst_RS(ir)]) +
- MIPSInst_SIMM(ir);
- unsigned int rt = MIPSInst_RT(ir) & ~1;
+ case swc1_op:{
+ u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
+ MIPSInst_SIMM(ir));
+ u32 val;
- fpuemuprivate.stats.stores++;
-#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__)
- if (put_user(ctx->regs[rt + 1], va + 0)
- || put_user(ctx->regs[rt + 0], va + 1))
- return SIGBUS;
-#else
- if (put_user(ctx->regs[rt + 0], va + 0)
- || put_user(ctx->regs[rt + 1], va + 1))
- return SIGBUS;
+ fpuemuprivate.stats.stores++;
+#ifdef SINGLE_ONLY_FPU
+ if (MIPSInst_RT(ir) & 1) {
+ /* illegal register in single-float mode */
+ return SIGILL;
+ }
#endif
+ SIFROMREG(val, MIPSInst_RT(ir));
+ if (put_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
}
break;
-#endif
+ }
case cop1_op:
switch (MIPSInst_RS(ir)) {
-#ifdef CP0_STATUS_FR_SUPPORT
#if __mips64 && !defined(SINGLE_ONLY_FPU)
case dmfc_op:
/* copregister fs -> gpr[rt] */
if (MIPSInst_RT(ir) != 0) {
- int fs = MIPSInst_RD(ir);
- if (!(regs->cp0_status & ST0_FR))
- fs &= ~1;
- regs->regs[MIPSInst_RT(ir)] = ctx->regs[fs];
+ DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
+ MIPSInst_RD(ir));
}
break;
- case dmtc_op: {
+ case dmtc_op:
/* copregister fs <- rt */
- fpureg_t value;
- int fs = MIPSInst_RD(ir);
- if (!(regs->cp0_status & ST0_FR))
- fs &= ~1;
- value =
- (MIPSInst_RT(ir) ==
- 0) ? 0 : regs->regs[MIPSInst_RT(ir)];
- ctx->regs[fs] = value;
+ DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
break;
- }
#endif
case mfc_op:
/* copregister rd -> gpr[rt] */
- if (MIPSInst_RT(ir) != 0) {
- /* default value from l.s. 32 bits */
- int value = ctx->regs[MIPSInst_RD(ir)];
- if (MIPSInst_RD(ir) & 1) {
#ifdef SINGLE_ONLY_FPU
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- if (!(regs->cp0_status & ST0_FR)) {
- /* move from m.s. 32 bits */
- value =
- ctx->
- regs[MIPSInst_RD(ir) &
- ~1] >> 32;
- }
-#endif
- }
- regs->regs[MIPSInst_RT(ir)] = value;
+ if (MIPSInst_RD(ir) & 1) {
+ /* illegal register in single-float mode */
+ return SIGILL;
}
- break;
-
- case mtc_op:
- /* copregister rd <- rt */
- {
- fpureg_t value;
- if (MIPSInst_RT(ir) == 0)
- value = 0;
- else
- value =
- (unsigned int) regs->
- regs[MIPSInst_RT(ir)];
- if (MIPSInst_RD(ir) & 1) {
-#ifdef SINGLE_ONLY_FPU
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- if (!(regs->cp0_status & ST0_FR)) {
- /* move to m.s. 32 bits */
- ctx->
- regs[
- (MIPSInst_RD(ir) &
- ~1)] &=
- 0xffffffff;
- ctx->
- regs[
- (MIPSInst_RD(ir) &
- ~1)] |=
- value << 32;
- break;
- }
#endif
- }
- /* move to l.s. 32 bits */
- ctx->regs[MIPSInst_RD(ir)] &=
- ~0xffffffffLL;
- ctx->regs[MIPSInst_RD(ir)] |= value;
- }
- break;
-#else
-
- case mfc_op:
- /* copregister rd -> gpr[rt] */
if (MIPSInst_RT(ir) != 0) {
- unsigned value =
- ctx->regs[MIPSInst_RD(ir)];
- regs->regs[MIPSInst_RT(ir)] = value;
+ SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
+ MIPSInst_RD(ir));
}
break;
case mtc_op:
/* copregister rd <- rt */
- {
- unsigned value;
- value =
- (MIPSInst_RT(ir) ==
- 0) ? 0 : regs->regs[MIPSInst_RT(ir)];
- ctx->regs[MIPSInst_RD(ir)] = value;
+#ifdef SINGLE_ONLY_FPU
+ if (MIPSInst_RD(ir) & 1) {
+ /* illegal register in single-float mode */
+ return SIGILL;
}
- break;
#endif
+ SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
+ break;
- case cfc_op:
+ case cfc_op:{
/* cop control register rd -> gpr[rt] */
- {
- unsigned value;
+ u32 value;
- if (MIPSInst_RD(ir) == FPCREG_CSR) {
- value = ctx->sr;
+ if (ir == CP1UNDEF) {
+ return do_dsemulret(xcp);
+ }
+ if (MIPSInst_RD(ir) == FPCREG_CSR) {
+ value = ctx->sr;
#ifdef CSRTRACE
- printk
- ("%p gpr[%d]<-csr=%08x\n",
- REG_TO_VA(regs->cp0_epc),
- MIPSInst_RT(ir), value);
+ printk("%p gpr[%d]<-csr=%08x\n",
+ REG_TO_VA(xcp->cp0_epc),
+ MIPSInst_RT(ir), value);
#endif
- } else if (MIPSInst_RD(ir) == FPCREG_RID)
- value = 0;
- else
- value = 0;
- if (MIPSInst_RT(ir))
- regs->regs[MIPSInst_RT(ir)] = value;
}
+ else if (MIPSInst_RD(ir) == FPCREG_RID)
+ value = 0;
+ else
+ value = 0;
+ if (MIPSInst_RT(ir))
+ xcp->regs[MIPSInst_RT(ir)] = value;
break;
+ }
- case ctc_op:
+ case ctc_op:{
/* copregister rd <- rt */
- {
- unsigned value;
-
- if (MIPSInst_RT(ir) == 0)
- value = 0;
- else
- value = regs->regs[MIPSInst_RT(ir)];
+ u32 value;
- /* we only have one writable control reg
- */
- if (MIPSInst_RD(ir) == FPCREG_CSR) {
+ if (MIPSInst_RT(ir) == 0)
+ value = 0;
+ else
+ value = xcp->regs[MIPSInst_RT(ir)];
+
+ /* we only have one writable control reg
+ */
+ if (MIPSInst_RD(ir) == FPCREG_CSR) {
#ifdef CSRTRACE
- printk
- ("%p gpr[%d]->csr=%08x\n",
- REG_TO_VA(regs->cp0_epc),
- MIPSInst_RT(ir), value);
-#endif
- ctx->sr = value;
- /* copy new rounding mode and
- flush bit to ieee library state! */
- ieee754_csr.nod =
- (ctx->sr & 0x1000000) != 0;
- ieee754_csr.rm =
- ieee_rm[value & 0x3];
- }
+ printk("%p gpr[%d]->csr=%08x\n",
+ REG_TO_VA(xcp->cp0_epc),
+ MIPSInst_RT(ir), value);
+#endif
+ ctx->sr = value;
+ /* copy new rounding mode and
+ flush bit to ieee library state! */
+ ieee754_csr.nod = (ctx->sr & 0x1000000) != 0;
+ ieee754_csr.rm = ieee_rm[value & 0x3];
+ }
+ if ((ctx->sr >> 5) & ctx->sr & FPU_CSR_ALL_E) {
+ return SIGFPE;
}
break;
+ }
- case bc_op: {
+ case bc_op:{
int likely = 0;
- if (regs->cp0_cause & CAUSEF_BD)
+ if (xcp->cp0_cause & CAUSEF_BD)
return SIGILL;
#if __mips >= 4
- cond = ctx-> sr & fpucondbit[MIPSInst_RT(ir) >> 2];
+ cond = ctx->sr & fpucondbit[MIPSInst_RT(ir) >> 2];
#else
cond = ctx->sr & FPU_CSR_COND;
#endif
@@ -593,16 +440,18 @@
return SIGILL;
}
- regs->cp0_cause |= CAUSEF_BD;
+ xcp->cp0_cause |= CAUSEF_BD;
if (cond) {
- /* branch taken: emulate dslot instruction */
- regs->cp0_epc += 4;
- contpc = REG_TO_VA regs->cp0_epc +
- (MIPSInst_SIMM(ir) << 2);
-
- err = get_user(ir,
- (mips_instruction *)regs->cp0_epc);
- if (err) {
+ /* branch taken: emulate dslot
+ * instruction
+ */
+ xcp->cp0_epc += 4;
+ contpc = REG_TO_VA
+ (xcp->cp0_epc +
+ (MIPSInst_SIMM(ir) << 2));
+
+ if (get_user(ir, (mips_instruction *)
+ REG_TO_VA xcp->cp0_epc)) {
fpuemuprivate.stats.errors++;
return SIGBUS;
}
@@ -629,49 +478,50 @@
}
/*
- * Single step the non-cp1 instruction in the
- * dslot
+ * Single step the non-cp1
+ * instruction in the dslot
*/
- return mips_dsemul(regs, ir, contpc);
- } else {
+ return mips_dsemul(xcp, ir, VA_TO_REG contpc);
+ }
+ else {
/* branch not taken */
if (likely) {
/*
- * branch likely nullifies dslot if not
- * taken
+ * branch likely nullifies
+ * dslot if not taken
*/
- regs->cp0_epc += 4;
+ xcp->cp0_epc += 4;
contpc += 4;
/*
- * else continue & execute dslot as
- * normal insn
+ * else continue & execute
+ * dslot as normal insn
*/
}
}
break;
}
- default: {
- int sig;
-
+ default:
if (!(MIPSInst_RS(ir) & 0x10))
return SIGILL;
+ {
+ int sig;
- /* a real fpu computation instruction */
- if ((sig = fpu_emu(regs, ctx, ir)))
+ /* a real fpu computation instruction */
+ if ((sig = fpu_emu(xcp, ctx, ir)))
return sig;
}
}
break;
#if __mips >= 4 && __mips != 32
- case cop1x_op:
- {
- int sig;
- if ((sig = fpux_emu(regs, ctx, ir)))
- return sig;
- }
+ case cop1x_op:{
+ int sig;
+
+ if ((sig = fpux_emu(xcp, ctx, ir)))
+ return sig;
break;
+ }
#endif
#if __mips >= 4
@@ -681,7 +531,7 @@
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
if (((ctx->sr & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0))
return 0;
- regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
+ xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
break;
#endif
@@ -690,194 +540,26 @@
}
/* we did it !! */
- regs->cp0_epc = VA_TO_REG(contpc);
- regs->cp0_cause &= ~CAUSEF_BD;
+ xcp->cp0_epc = VA_TO_REG(contpc);
+ xcp->cp0_cause &= ~CAUSEF_BD;
return 0;
}
/*
- * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
- * we have to emulate the instruction in a COP1 branch delay slot. Do
- * not change cp0_epc due to the instruction
- *
- * According to the spec:
- * 1) it shouldnt be a branch :-)
- * 2) it can be a COP instruction :-(
- * 3) if we are tring to run a protected memory space we must take
- * special care on memory access instructions :-(
- */
-
-/*
- * "Trampoline" return routine to catch exception following
- * execution of delay-slot instruction execution.
- */
-
-/* Instruction inserted following delay slot instruction to force trap */
-#define AdELOAD 0x8c000001 /* lw $0,1($0) */
-
-/* Instruction inserted following the AdELOAD to further tag the sequence */
-#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */
-
-struct emuframe {
- mips_instruction emul;
- mips_instruction adel;
- mips_instruction cookie;
- unsigned long epc;
-};
-
-int do_dsemulret(struct pt_regs *xcp)
-{
- struct emuframe *fr;
- unsigned long epc;
- u32 insn, cookie;
- int err = 0;
-
- fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction));
-
- /*
- * If we can't even access the area, something is very wrong, but we'll
- * leave that to the default handling
- */
- if (verify_area(VERIFY_READ, fr, sizeof(struct emuframe)))
- return 0;
-
- /*
- * Do some sanity checking on the stackframe:
- *
- * - Is the instruction pointed to by the EPC an AdELOAD?
- * - Is the following memory word the BD_COOKIE?
- */
- err = __get_user(insn, &fr->adel);
- err |= __get_user(cookie, &fr->cookie);
-
- if (unlikely(err || (insn != AdELOAD) || (cookie != BD_COOKIE))) {
- fpuemuprivate.stats.errors++;
-
- return 0;
- }
-
- /*
- * At this point, we are satisfied that it's a BD emulation trap. Yes,
- * a user might have deliberately put two malformed and useless
- * instructions in a row in his program, in which case he's in for a
- * nasty surprise - the next instruction will be treated as a
- * continuation address! Alas, this seems to be the only way that we
- * can handle signals, recursion, and longjmps() in the context of
- * emulating the branch delay instruction.
- */
-
-#ifdef DSEMUL_TRACE
- printk("desemulret\n");
-#endif
- if (__get_user(epc, &fr->epc)) { /* Saved EPC */
- /* This is not a good situation to be in */
- force_sig(SIGBUS, current);
-
- return 1;
- }
-
- /* Set EPC to return to post-branch instruction */
- xcp->cp0_epc = epc;
-
- return 1;
-}
-
-static int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
- unsigned long cpc)
-{
- extern asmlinkage void handle_dsemulret(void);
- mips_instruction *dsemul_insns;
- struct emuframe *fr;
- int err;
-
- if (ir == 0) { /* a nop is easy */
- regs->cp0_epc = cpc;
- regs->cp0_cause &= ~CAUSEF_BD;
- return 0;
- }
-#ifdef DSEMUL_TRACE
- printk("desemul %lx %lx\n", regs->cp0_epc, cpc);
-
-#endif
-
- /*
- * The strategy is to push the instruction onto the user stack
- * and put a trap after it which we can catch and jump to
- * the required address any alternative apart from full
- * instruction emulation!!.
- *
- * Algorithmics used a system call instruction, and
- * borrowed that vector. MIPS/Linux version is a bit
- * more heavyweight in the interests of portability and
- * multiprocessor support. We flag the thread for special
- * handling in the unaligned access handler and force an
- * address error excpetion.
- */
-
- /* Ensure that the two instructions are in the same cache line */
- dsemul_insns = (mips_instruction *) (regs->regs[29] & ~0xf);
- dsemul_insns -= 4; /* Retain 16-byte alignment */
- fr = (struct emuframe *) dsemul_insns;
-
- /* Verify that the stack pointer is not competely insane */
- if (unlikely(verify_area(VERIFY_WRITE, fr, sizeof(struct emuframe))))
- return SIGBUS;
-
- err = __put_user(ir, &dsemul_insns[0]);
- err |= __put_user((mips_instruction)AdELOAD, &fr->adel);
- err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
- err |= __put_user(cpc, &fr->epc);
-
- if (unlikely(err)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
-
- regs->cp0_epc = VA_TO_REG & dsemul_insns[0];
-
- flush_cache_sigtramp((unsigned long)&fr->adel);
-
- return SIGILL; /* force out of emulation loop */
-}
-
-/*
* Conversion table from MIPS compare ops 48-63
- * cond = ieee754dp_cmp(x,y,IEEE754_UN);
+ * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
*/
static const unsigned char cmptab[8] = {
- 0, /* cmp_0 (sig) cmp_sf */
- IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
- IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
- IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
- IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
- IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
- IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
- IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
+ 0, /* cmp_0 (sig) cmp_sf */
+ IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
+ IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
+ IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
+ IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
+ IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
+ IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
+ IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
};
-#define SIFROMREG(si,x) ((si) = ctx->regs[x])
-#define SITOREG(si,x) (ctx->regs[x] = (int)(si))
-
-#if __mips64 && !defined(SINGLE_ONLY_FPU)
-#define DIFROMREG(di,x) ((di) = ctx->regs[x])
-#define DITOREG(di,x) (ctx->regs[x] = (di))
-#endif
-
-#define SPFROMREG(sp,x) ((sp).bits = ctx->regs[x])
-#define SPTOREG(sp,x) (ctx->regs[x] = (sp).bits)
-
-#ifdef CP0_STATUS_FR_SUPPORT
-#define DPFROMREG(dp,x) ((dp).bits = \
- ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)])
-#define DPTOREG(dp,x) (ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)] \
- = (dp).bits)
-#else
-/* Beware: MIPS COP1 doubles are always little_word endian in registers */
-#define DPFROMREG(dp,x) \
- ((dp).bits = ((u64)ctx->regs[(x)+1] << 32) | ctx->regs[x])
-#define DPTOREG(dp,x) \
- (ctx->regs[x] = (dp).bits, ctx->regs[(x)+1] = (dp).bits >> 32)
-#endif
#if __mips >= 4 && __mips != 32
@@ -889,17 +571,17 @@
static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
ieee754##p t) \
{ \
- struct ieee754_csr ieee754_csr_save; \
- s = f1 (s, t); \
- ieee754_csr_save = ieee754_csr; \
- s = f2 (s, r); \
- ieee754_csr_save.cx |= ieee754_csr.cx; \
- ieee754_csr_save.sx |= ieee754_csr.sx; \
- s = f3 (s); \
- ieee754_csr.cx |= ieee754_csr_save.cx; \
- ieee754_csr.sx |= ieee754_csr_save.sx; \
- return s; \
-}
+ struct ieee754_csr ieee754_csr_save; \
+ s = f1 (s, t); \
+ ieee754_csr_save = ieee754_csr; \
+ s = f2 (s, r); \
+ ieee754_csr_save.cx |= ieee754_csr.cx; \
+ ieee754_csr_save.sx |= ieee754_csr.sx; \
+ s = f3 (s); \
+ ieee754_csr.cx |= ieee754_csr_save.cx; \
+ ieee754_csr.sx |= ieee754_csr_save.sx; \
+ return s; \
+}
static ieee754dp fpemu_dp_recip(ieee754dp d)
{
@@ -921,233 +603,184 @@
return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
}
-DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
-DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
+DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,);
+DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,);
DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
-DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
-DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
+DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,);
+DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
- mips_instruction ir)
+ mips_instruction ir)
{
unsigned rcsr = 0; /* resulting csr */
fpuemuprivate.stats.cp1xops++;
switch (MIPSInst_FMA_FFMT(ir)) {
- case s_fmt: /* 0 */
- {
- ieee754sp(*handler) (ieee754sp, ieee754sp,
- ieee754sp);
- ieee754sp fd, fr, fs, ft;
-
- switch (MIPSInst_FUNC(ir)) {
- case lwxc1_op:
- {
- u32 *va = REG_TO_VA(
- xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
- fpureg_t val;
-
- if (get_user(val, va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- if (xcp->cp0_status & ST0_FR) {
- /* load whole register */
- ctx->regs[MIPSInst_FD(ir)] =
- val;
- } else if (MIPSInst_FD(ir) & 1) {
- /* load to m.s. 32 bits */
-#if defined(SINGLE_ONLY_FPU)
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- ctx->
- regs[
- (MIPSInst_FD(ir) &
- ~1)] &=
- 0xffffffff;
- ctx->
- regs[
- (MIPSInst_FD(ir) &
- ~1)] |=
- val << 32;
-#endif
- } else {
- /* load to l.s. 32 bits */
- ctx->
- regs[MIPSInst_FD(ir)]
- &= ~0xffffffffLL;
- ctx->
- regs[MIPSInst_FD(ir)]
- |= val;
- }
- }
- break;
+ case s_fmt:{ /* 0 */
- case swxc1_op:
- {
- u32 *va = REG_TO_VA(
- xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
- unsigned int val;
-
- if (xcp->cp0_status & ST0_FR) {
- /* store whole register */
- val = ctx->regs[MIPSInst_FS(ir)];
- } else if (MIPSInst_FS(ir) & 1) {
-#if defined(SINGLE_ONLY_FPU)
- /* illegal register in single-float mode */
- return SIGILL;
-#else
- /* store from m.s. 32 bits */
- val = ctx->regs[(MIPSInst_FS(ir) & ~1)] >> 32;
+ ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
+ ieee754sp fd, fr, fs, ft;
+ u32 *va;
+ u32 val;
+
+ switch (MIPSInst_FUNC(ir)) {
+ case lwxc1_op:
+ va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
+ xcp->regs[MIPSInst_FT(ir)]);
+
+ fpuemuprivate.stats.loads++;
+ if (get_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
+ }
+#ifdef SINGLE_ONLY_FPU
+ if (MIPSInst_FD(ir) & 1) {
+ /* illegal register in single-float
+ * mode
+ */
+ return SIGILL;
+ }
#endif
- } else {
- /* store from l.s. 32 bits */
- val =
- ctx->
- regs[MIPSInst_FS(ir)];
- }
- if (put_user(val, va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- }
- break;
+ SITOREG(val, MIPSInst_FD(ir));
+ break;
- case madd_s_op:
- handler = fpemu_sp_madd;
- goto scoptop;
- case msub_s_op:
- handler = fpemu_sp_msub;
- goto scoptop;
- case nmadd_s_op:
- handler = fpemu_sp_nmadd;
- goto scoptop;
- case nmsub_s_op:
- handler = fpemu_sp_nmsub;
- goto scoptop;
+ case swxc1_op:
+ va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
+ xcp->regs[MIPSInst_FT(ir)]);
- scoptop:
- SPFROMREG(fr, MIPSInst_FR(ir));
- SPFROMREG(fs, MIPSInst_FS(ir));
- SPFROMREG(ft, MIPSInst_FT(ir));
- fd = (*handler) (fr, fs, ft);
- SPTOREG(fd, MIPSInst_FD(ir));
+ fpuemuprivate.stats.stores++;
+#ifdef SINGLE_ONLY_FPU
+ if (MIPSInst_FS(ir) & 1) {
+ /* illegal register in single-float
+ * mode
+ */
+ return SIGILL;
+ }
+#endif
- copcsr:
- if (ieee754_cxtest(IEEE754_INEXACT))
- rcsr |=
- FPU_CSR_INE_X | FPU_CSR_INE_S;
- if (ieee754_cxtest(IEEE754_UNDERFLOW))
- rcsr |=
- FPU_CSR_UDF_X | FPU_CSR_UDF_S;
- if (ieee754_cxtest(IEEE754_OVERFLOW))
- rcsr |=
- FPU_CSR_OVF_X | FPU_CSR_OVF_S;
- if (ieee754_cxtest
- (IEEE754_INVALID_OPERATION)) rcsr |=
- FPU_CSR_INV_X | FPU_CSR_INV_S;
-
- ctx->sr =
- (ctx->sr & ~FPU_CSR_ALL_X) | rcsr;
- if (ieee754_csr.nod)
- ctx->sr |= 0x1000000;
- if ((ctx->sr >> 5) & ctx->
- sr & FPU_CSR_ALL_E) {
- /*printk ("SIGFPE: fpu csr = %08x\n",ctx->sr); */
- return SIGFPE;
- }
+ SIFROMREG(val, MIPSInst_FS(ir));
+ if (put_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
+ }
+ break;
- break;
+ case madd_s_op:
+ handler = fpemu_sp_madd;
+ goto scoptop;
+ case msub_s_op:
+ handler = fpemu_sp_msub;
+ goto scoptop;
+ case nmadd_s_op:
+ handler = fpemu_sp_nmadd;
+ goto scoptop;
+ case nmsub_s_op:
+ handler = fpemu_sp_nmsub;
+ goto scoptop;
- default:
- return SIGILL;
+ scoptop:
+ SPFROMREG(fr, MIPSInst_FR(ir));
+ SPFROMREG(fs, MIPSInst_FS(ir));
+ SPFROMREG(ft, MIPSInst_FT(ir));
+ fd = (*handler) (fr, fs, ft);
+ SPTOREG(fd, MIPSInst_FD(ir));
+
+ copcsr:
+ if (ieee754_cxtest(IEEE754_INEXACT))
+ rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
+ if (ieee754_cxtest(IEEE754_UNDERFLOW))
+ rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
+ if (ieee754_cxtest(IEEE754_OVERFLOW))
+ rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
+ if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
+ rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
+
+ ctx->sr = (ctx->sr & ~FPU_CSR_ALL_X) | rcsr;
+ if (ieee754_csr.nod)
+ ctx->sr |= 0x1000000;
+ if ((ctx->sr >> 5) & ctx->sr & FPU_CSR_ALL_E) {
+ /*printk ("SIGFPE: fpu csr = %08x\n",
+ ctx->sr); */
+ return SIGFPE;
}
+
+ break;
+
+ default:
+ return SIGILL;
}
break;
+ }
-#if !defined(SINGLE_ONLY_FPU)
- case d_fmt: /* 1 */
- {
- ieee754dp(*handler) (ieee754dp, ieee754dp,
- ieee754dp);
- ieee754dp fd, fr, fs, ft;
-
- switch (MIPSInst_FUNC(ir)) {
- case ldxc1_op:
- {
- u64 *va = REG_TO_VA(
- xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
- u64 val;
-
- if (get_user(val, va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- ctx->regs[MIPSInst_FD(ir)] = val;
- }
- break;
+#ifndef SINGLE_ONLY_FPU
+ case d_fmt:{ /* 1 */
+ ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
+ ieee754dp fd, fr, fs, ft;
+ u64 *va;
+ u64 val;
- case sdxc1_op:
- {
- u64 *va = REG_TO_VA(
- xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
- u64 val;
-
- val = ctx->regs[MIPSInst_FS(ir)];
- if (put_user(val, va)) {
- fpuemuprivate.stats.errors++;
- return SIGBUS;
- }
- }
- break;
+ switch (MIPSInst_FUNC(ir)) {
+ case ldxc1_op:
+ va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
+ xcp->regs[MIPSInst_FT(ir)]);
- case madd_d_op:
- handler = fpemu_dp_madd;
- goto dcoptop;
-
- case msub_d_op:
- handler = fpemu_dp_msub;
- goto dcoptop;
-
- case nmadd_d_op:
- handler = fpemu_dp_nmadd;
- goto dcoptop;
-
- case nmsub_d_op:
- handler = fpemu_dp_nmsub;
- goto dcoptop;
+ fpuemuprivate.stats.loads++;
+ if (get_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
+ }
+ DITOREG(val, MIPSInst_FD(ir));
+ break;
- dcoptop:
- DPFROMREG(fr, MIPSInst_FR(ir));
- DPFROMREG(fs, MIPSInst_FS(ir));
- DPFROMREG(ft, MIPSInst_FT(ir));
- fd = (*handler) (fr, fs, ft);
- DPTOREG(fd, MIPSInst_FD(ir));
- goto copcsr;
+ case sdxc1_op:
+ va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
+ xcp->regs[MIPSInst_FT(ir)]);
- default:
- return SIGILL;
+ fpuemuprivate.stats.stores++;
+ DIFROMREG(val, MIPSInst_FS(ir));
+ if (put_user(val, va)) {
+ fpuemuprivate.stats.errors++;
+ return SIGBUS;
}
+ break;
+
+ case madd_d_op:
+ handler = fpemu_dp_madd;
+ goto dcoptop;
+ case msub_d_op:
+ handler = fpemu_dp_msub;
+ goto dcoptop;
+ case nmadd_d_op:
+ handler = fpemu_dp_nmadd;
+ goto dcoptop;
+ case nmsub_d_op:
+ handler = fpemu_dp_nmsub;
+ goto dcoptop;
+
+ dcoptop:
+ DPFROMREG(fr, MIPSInst_FR(ir));
+ DPFROMREG(fs, MIPSInst_FS(ir));
+ DPFROMREG(ft, MIPSInst_FT(ir));
+ fd = (*handler) (fr, fs, ft);
+ DPTOREG(fd, MIPSInst_FD(ir));
+ goto copcsr;
+
+ default:
+ return SIGILL;
}
break;
+ }
#endif
case 0x7: /* 7 */
- {
- if (MIPSInst_FUNC(ir) != pfetch_op) {
- return SIGILL;
- }
- /* ignore prefx operation */
+ if (MIPSInst_FUNC(ir) != pfetch_op) {
+ return SIGILL;
}
+ /* ignore prefx operation */
break;
default:
@@ -1164,7 +797,7 @@
* Emulate a single COP1 arithmetic instruction.
*/
static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
- mips_instruction ir)
+ mips_instruction ir)
{
int rfmt; /* resulting format */
unsigned rcsr = 0; /* resulting csr */
@@ -1174,49 +807,52 @@
ieee754sp s;
int w;
#if __mips64
- long long l;
+ s64 l;
#endif
} rv; /* resulting value */
fpuemuprivate.stats.cp1ops++;
switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
- case s_fmt: { /* 0 */
- ieee754sp(*handler) ();
+ case s_fmt:{ /* 0 */
+ union {
+ ieee754sp(*b) (ieee754sp, ieee754sp);
+ ieee754sp(*u) (ieee754sp);
+ } handler;
switch (MIPSInst_FUNC(ir)) {
/* binary ops */
case fadd_op:
- handler = ieee754sp_add;
+ handler.b = ieee754sp_add;
goto scopbop;
case fsub_op:
- handler = ieee754sp_sub;
+ handler.b = ieee754sp_sub;
goto scopbop;
case fmul_op:
- handler = ieee754sp_mul;
+ handler.b = ieee754sp_mul;
goto scopbop;
case fdiv_op:
- handler = ieee754sp_div;
+ handler.b = ieee754sp_div;
goto scopbop;
/* unary ops */
#if __mips >= 2 || __mips64
case fsqrt_op:
- handler = ieee754sp_sqrt;
+ handler.u = ieee754sp_sqrt;
goto scopuop;
#endif
#if __mips >= 4 && __mips != 32
case frsqrt_op:
- handler = fpemu_sp_rsqrt;
+ handler.u = fpemu_sp_rsqrt;
goto scopuop;
case frecip_op:
- handler = fpemu_sp_recip;
+ handler.u = fpemu_sp_recip;
goto scopuop;
#endif
#if __mips >= 4
case fmovc_op:
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
if (((ctx->sr & cond) != 0) !=
- ((MIPSInst_FT(ir) & 1) != 0))
+ ((MIPSInst_FT(ir) & 1) != 0))
return 0;
SPFROMREG(rv.s, MIPSInst_FS(ir));
break;
@@ -1232,10 +868,10 @@
break;
#endif
case fabs_op:
- handler = ieee754sp_abs;
+ handler.u = ieee754sp_abs;
goto scopuop;
case fneg_op:
- handler = ieee754sp_neg;
+ handler.u = ieee754sp_neg;
goto scopuop;
case fmov_op:
/* an easy one */
@@ -1243,25 +879,25 @@
goto copcsr;
/* binary op on handler */
-scopbop:
+ scopbop:
{
ieee754sp fs, ft;
SPFROMREG(fs, MIPSInst_FS(ir));
SPFROMREG(ft, MIPSInst_FT(ir));
- rv.s = (*handler) (fs, ft);
+ rv.s = (*handler.b) (fs, ft);
goto copcsr;
}
-scopuop:
+ scopuop:
{
ieee754sp fs;
SPFROMREG(fs, MIPSInst_FS(ir));
- rv.s = (*handler) (fs);
+ rv.s = (*handler.u) (fs);
goto copcsr;
}
-copcsr:
+ copcsr:
if (ieee754_cxtest(IEEE754_INEXACT))
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
if (ieee754_cxtest(IEEE754_UNDERFLOW))
@@ -1270,15 +906,14 @@
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
- if (ieee754_cxtest
- (IEEE754_INVALID_OPERATION)) rcsr |=
- FPU_CSR_INV_X | FPU_CSR_INV_S;
- break;
+ if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
+ rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
+ break;
- /* unary conv ops */
+ /* unary conv ops */
case fcvts_op:
return SIGILL; /* not defined */
- case fcvtd_op: {
+ case fcvtd_op:{
#ifdef SINGLE_ONLY_FPU
return SIGILL; /* not defined */
#else
@@ -1290,7 +925,7 @@
goto copcsr;
}
#endif
- case fcvtw_op: {
+ case fcvtw_op:{
ieee754sp fs;
SPFROMREG(fs, MIPSInst_FS(ir));
@@ -1303,7 +938,7 @@
case fround_op:
case ftrunc_op:
case fceil_op:
- case ffloor_op: {
+ case ffloor_op:{
unsigned int oldrm = ieee754_csr.rm;
ieee754sp fs;
@@ -1317,7 +952,7 @@
#endif /* __mips >= 2 */
#if __mips64 && !defined(SINGLE_ONLY_FPU)
- case fcvtl_op: {
+ case fcvtl_op:{
ieee754sp fs;
SPFROMREG(fs, MIPSInst_FS(ir));
@@ -1329,7 +964,7 @@
case froundl_op:
case ftruncl_op:
case fceill_op:
- case ffloorl_op: {
+ case ffloorl_op:{
unsigned int oldrm = ieee754_csr.rm;
ieee754sp fs;
@@ -1349,14 +984,17 @@
SPFROMREG(fs, MIPSInst_FS(ir));
SPFROMREG(ft, MIPSInst_FT(ir));
- rv.w = ieee754sp_cmp(fs, ft, cmptab[cmpop & 0x7]);
+ rv.w = ieee754sp_cmp(fs, ft,
+ cmptab[cmpop & 0x7], cmpop & 0x8);
rfmt = -1;
- if ((cmpop & 0x8) && ieee754_cxtest(IEEE754_INVALID_OPERATION))
+ if ((cmpop & 0x8) && ieee754_cxtest
+ (IEEE754_INVALID_OPERATION))
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
else
goto copcsr;
- } else {
+ }
+ else {
return SIGILL;
}
break;
@@ -1364,43 +1002,47 @@
break;
}
-#if !defined(SINGLE_ONLY_FPU)
- case d_fmt: {
- ieee754dp(*handler) ();
+#ifndef SINGLE_ONLY_FPU
+ case d_fmt:{
+ union {
+ ieee754dp(*b) (ieee754dp, ieee754dp);
+ ieee754dp(*u) (ieee754dp);
+ } handler;
switch (MIPSInst_FUNC(ir)) {
/* binary ops */
case fadd_op:
- handler = ieee754dp_add;
+ handler.b = ieee754dp_add;
goto dcopbop;
case fsub_op:
- handler = ieee754dp_sub;
+ handler.b = ieee754dp_sub;
goto dcopbop;
case fmul_op:
- handler = ieee754dp_mul;
+ handler.b = ieee754dp_mul;
goto dcopbop;
case fdiv_op:
- handler = ieee754dp_div;
+ handler.b = ieee754dp_div;
goto dcopbop;
/* unary ops */
#if __mips >= 2 || __mips64
case fsqrt_op:
- handler = ieee754dp_sqrt;
+ handler.u = ieee754dp_sqrt;
goto dcopuop;
#endif
#if __mips >= 4 && __mips != 32
case frsqrt_op:
- handler = fpemu_dp_rsqrt;
+ handler.u = fpemu_dp_rsqrt;
goto dcopuop;
case frecip_op:
- handler = fpemu_dp_recip;
+ handler.u = fpemu_dp_recip;
goto dcopuop;
#endif
#if __mips >= 4
case fmovc_op:
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
- if (((ctx->sr & cond) != 0) != ((MIPSInst_FT(ir) & 1) != 0))
+ if (((ctx->sr & cond) != 0) !=
+ ((MIPSInst_FT(ir) & 1) != 0))
return 0;
DPFROMREG(rv.d, MIPSInst_FS(ir));
break;
@@ -1416,11 +1058,11 @@
break;
#endif
case fabs_op:
- handler = ieee754dp_abs;
+ handler.u = ieee754dp_abs;
goto dcopuop;
case fneg_op:
- handler = ieee754dp_neg;
+ handler.u = ieee754dp_neg;
goto dcopuop;
case fmov_op:
@@ -1429,27 +1071,25 @@
goto copcsr;
/* binary op on handler */
-dcopbop:
- {
+ dcopbop:{
ieee754dp fs, ft;
DPFROMREG(fs, MIPSInst_FS(ir));
DPFROMREG(ft, MIPSInst_FT(ir));
- rv.d = (*handler) (fs, ft);
+ rv.d = (*handler.b) (fs, ft);
goto copcsr;
}
-dcopuop:
- {
+ dcopuop:{
ieee754dp fs;
DPFROMREG(fs, MIPSInst_FS(ir));
- rv.d = (*handler) (fs);
+ rv.d = (*handler.u) (fs);
goto copcsr;
}
- /* unary conv ops */
- case fcvts_op: {
+ /* unary conv ops */
+ case fcvts_op:{
ieee754dp fs;
DPFROMREG(fs, MIPSInst_FS(ir));
@@ -1460,7 +1100,7 @@
case fcvtd_op:
return SIGILL; /* not defined */
- case fcvtw_op: {
+ case fcvtw_op:{
ieee754dp fs;
DPFROMREG(fs, MIPSInst_FS(ir));
@@ -1473,7 +1113,7 @@
case fround_op:
case ftrunc_op:
case fceil_op:
- case ffloor_op: {
+ case ffloor_op:{
unsigned int oldrm = ieee754_csr.rm;
ieee754dp fs;
@@ -1487,7 +1127,7 @@
#endif
#if __mips64 && !defined(SINGLE_ONLY_FPU)
- case fcvtl_op: {
+ case fcvtl_op:{
ieee754dp fs;
DPFROMREG(fs, MIPSInst_FS(ir));
@@ -1499,7 +1139,7 @@
case froundl_op:
case ftruncl_op:
case fceill_op:
- case ffloorl_op: {
+ case ffloorl_op:{
unsigned int oldrm = ieee754_csr.rm;
ieee754dp fs;
@@ -1519,33 +1159,42 @@
DPFROMREG(fs, MIPSInst_FS(ir));
DPFROMREG(ft, MIPSInst_FT(ir));
- rv.w = ieee754dp_cmp(fs, ft, cmptab[cmpop & 0x7]);
+ rv.w = ieee754dp_cmp(fs, ft,
+ cmptab[cmpop & 0x7], cmpop & 0x8);
rfmt = -1;
- if ((cmpop & 0x8) && ieee754_cxtest (IEEE754_INVALID_OPERATION))
+ if ((cmpop & 0x8)
+ &&
+ ieee754_cxtest
+ (IEEE754_INVALID_OPERATION))
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
else
goto copcsr;
- } else {
+ }
+ else {
return SIGILL;
}
break;
}
break;
}
-#endif /* !defined(SINGLE_ONLY_FPU) */
+#endif /* ifndef SINGLE_ONLY_FPU */
+
+ case w_fmt:{
+ ieee754sp fs;
- case w_fmt: {
switch (MIPSInst_FUNC(ir)) {
case fcvts_op:
/* convert word to single precision real */
- rv.s = ieee754sp_fint(ctx-> regs[MIPSInst_FS(ir)]);
+ SPFROMREG(fs, MIPSInst_FS(ir));
+ rv.s = ieee754sp_fint(fs.bits);
rfmt = s_fmt;
goto copcsr;
-#if !defined(SINGLE_ONLY_FPU)
+#ifndef SINGLE_ONLY_FPU
case fcvtd_op:
/* convert word to double precision real */
- rv.d = ieee754dp_fint(ctx-> regs[MIPSInst_FS(ir)]);
+ SPFROMREG(fs, MIPSInst_FS(ir));
+ rv.d = ieee754dp_fint(fs.bits);
rfmt = d_fmt;
goto copcsr;
#endif
@@ -1556,16 +1205,16 @@
}
#if __mips64 && !defined(SINGLE_ONLY_FPU)
- case l_fmt: {
+ case l_fmt:{
switch (MIPSInst_FUNC(ir)) {
case fcvts_op:
/* convert long to single precision real */
- rv.s = ieee754sp_flong(ctx-> regs[MIPSInst_FS(ir)]);
+ rv.s = ieee754sp_flong(ctx->regs[MIPSInst_FS(ir)]);
rfmt = s_fmt;
goto copcsr;
case fcvtd_op:
/* convert long to double precision real */
- rv.d = ieee754dp_flong(ctx-> regs[MIPSInst_FS(ir)]);
+ rv.d = ieee754dp_flong(ctx->regs[MIPSInst_FS(ir)]);
rfmt = d_fmt;
goto copcsr;
default:
@@ -1592,11 +1241,11 @@
return SIGFPE;
}
- /*
+ /*
* Now we can safely write the result back to the register file.
*/
switch (rfmt) {
- case -1: {
+ case -1:{
#if __mips >= 4
cond = fpucondbit[MIPSInst_FD(ir) >> 2];
#else
@@ -1608,7 +1257,7 @@
ctx->sr &= ~cond;
break;
}
-#if !defined(SINGLE_ONLY_FPU)
+#ifndef SINGLE_ONLY_FPU
case d_fmt:
DPTOREG(rv.d, MIPSInst_FD(ir));
break;
@@ -1631,16 +1280,10 @@
return 0;
}
-
-/*
- * Emulate the floating point instruction at EPC, and continue to run until we
- * hit a non-fp instruction, or a backward branch. This cuts down dramatically
- * on the per instruction exception overhead.
- */
-int fpu_emulator_cop1Handler(struct pt_regs *xcp)
+int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
+ struct mips_fpu_soft_struct *ctx)
{
- struct mips_fpu_soft_struct *ctx = ¤t->thread.fpu.soft;
- unsigned long oldepc, prevepc;
+ gpreg_t oldepc, prevepc;
mips_instruction insn, *insnp;
int sig = 0;
@@ -1652,9 +1295,10 @@
* This is a braindead way to do it but the only sane way I
* found to keep the 64-bit egcs 1.1.2 from crashing.
*/
- insnp = (mips_instruction *) xcp->cp0_epc;
+ insnp = (mips_instruction *) REG_TO_VA xcp->cp0_epc;
+
if (verify_area(VERIFY_READ, insnp, 4) ||
- __get_user(insn, insnp)) {
+ __get_user(insn, insnp)) {
fpuemuprivate.stats.errors++;
return SIGBUS;
}
@@ -1673,9 +1317,13 @@
break;
if (sig)
break;
-
+#ifdef STANDALONE_EMULATOR
+ if (xcptno == EX_FPE)
+ break;
+#else
if (current->need_resched)
schedule();
+#endif
} while (xcp->cp0_epc > prevepc);
/* SIGILL indicates a non-fpu instruction */
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)