patch-2.4.19 linux-2.4.19/include/asm-mips/mipsregs.h
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- Lines: 833
- Date:
Fri Aug 2 17:39:45 2002
- Orig file:
linux-2.4.18/include/asm-mips/mipsregs.h
- Orig date:
Sun Sep 9 10:43:01 2001
diff -urN linux-2.4.18/include/asm-mips/mipsregs.h linux-2.4.19/include/asm-mips/mipsregs.h
@@ -12,6 +12,7 @@
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
+#include <linux/config.h>
#include <linux/linkage.h>
/*
@@ -52,12 +53,15 @@
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
/*
* R4640/R4650 cp0 register names. These registers are listed
@@ -79,6 +83,12 @@
#define CP0_S1_DERRADDR0 $26
#define CP0_S1_DERRADDR1 $27
#define CP0_S1_INTCONTROL $20
+
+/*
+ * TX39 Series
+ */
+#define CP0_TX39_CACHE $7
+
/*
* Coprocessor 1 (FPU) register names
*/
@@ -140,102 +150,42 @@
/*
* Values for PageMask register
*/
-#include <linux/config.h>
#ifdef CONFIG_CPU_VR41XX
-#define PM_1K 0x00000000
-#define PM_4K 0x00001800
-#define PM_16K 0x00007800
-#define PM_64K 0x0001f800
-#define PM_256K 0x0007f800
-#else
-#define PM_4K 0x00000000
-#define PM_16K 0x00006000
-#define PM_64K 0x0001e000
-#define PM_256K 0x0007e000
-#define PM_1M 0x001fe000
-#define PM_4M 0x007fe000
-#define PM_16M 0x01ffe000
-#endif
-
-/*
- * Values used for computation of new tlb entries
- */
-#define PL_4K 12
-#define PL_16K 14
-#define PL_64K 16
-#define PL_256K 18
-#define PL_1M 20
-#define PL_4M 22
-#define PL_16M 24
-
-/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "mfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-#define read_32bit_cp0_set1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+/* Why doesn't stupidity hurt ... */
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
+#define PM_1K 0x00000000
+#define PM_4K 0x00001800
+#define PM_16K 0x00007800
+#define PM_64K 0x0001f800
+#define PM_256K 0x0007f800
-#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
+#else
-#define write_32bit_cp0_set1_register(register,value) \
- __asm__ __volatile__( \
- "ctc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
+#define PM_4K 0x00000000
+#define PM_16K 0x00006000
+#define PM_64K 0x0001e000
+#define PM_256K 0x0007e000
+#define PM_1M 0x001fe000
+#define PM_4M 0x007fe000
+#define PM_16M 0x01ffe000
+#define PM_64M 0x07ffe000
+#define PM_256M 0x1fffe000
-#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
+#endif
-/*
- * This should be changed when we get a compiler that support the MIPS32 ISA.
+/*
+ * Values used for computation of new tlb entries
*/
-#define read_mips32_cp0_config1() \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n\t" \
- ".word\t0x40018001\n\t" \
- "move\t%0,$1\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
- :"=r" (__res)); \
- __res;})
+#define PL_4K 12
+#define PL_16K 14
+#define PL_64K 16
+#define PL_256K 18
+#define PL_1M 20
+#define PL_4M 22
+#define PL_16M 24
+#define PL_64M 26
+#define PL_256M 28
/*
* R4x00 interrupt enable / cause bits
@@ -261,56 +211,6 @@
#define C_IRQ4 (1<<14)
#define C_IRQ5 (1<<15)
-#ifndef _LANGUAGE_ASSEMBLY
-/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register) \
-extern __inline__ unsigned int \
-set_cp0_##name(unsigned int set) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res |= set; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern __inline__ unsigned int \
-clear_cp0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~clear; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern __inline__ unsigned int \
-change_cp0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~change; \
- res |= (new & change); \
- if(change) \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
-
/*
* Bitfields in the R4xx0 cp0 status register
*/
@@ -419,6 +319,7 @@
#define STATUSF_IP15 (1 << 7)
#define ST0_CH 0x00040000
#define ST0_SR 0x00100000
+#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
#define ST0_RE 0x02000000
#define ST0_FR 0x04000000
@@ -480,6 +381,14 @@
#define CONF_HALT (1 << 25)
/*
+ * Bits in the TX49 coprozessor 0 config register.
+ */
+#define TX49_CONF_DC (1 << 16)
+#define TX49_CONF_IC (1 << 17) /* conflict with CONF_SC */
+#define TX49_CONF_HALT (1 << 18)
+#define TX49_CONF_CWFON (1 << 27)
+
+/*
* R10000 performance counter definitions.
*
* FIXME: The R10000 performance counter opens a nice way to implement CPU
@@ -535,4 +444,584 @@
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+#ifndef __ASSEMBLY__
+
+/*
+ * Functions to access the r10k performance counter and control registers
+ */
+#define read_r10k_perf_cntr(counter) \
+({ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfpc\t%0, "STR(counter) \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_r10k_perf_cntr(counter,val) \
+ __asm__ __volatile__( \
+ "mtpc\t%0, "STR(counter) \
+ : : "r" (val));
+
+#define read_r10k_perf_cntl(counter) \
+({ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfps\t%0, "STR(counter) \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_r10k_perf_cntl(counter,val) \
+ __asm__ __volatile__( \
+ "mtps\t%0, "STR(counter) \
+ : : "r" (val));
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "mfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define read_32bit_cp0_set1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source) \
+({ unsigned long __res; \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value) \
+ __asm__ __volatile__( \
+ "ctc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_64bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1() \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tnoreorder\n\t" \
+ ".set\tnoat\n\t" \
+ "#.set\tmips64\n\t" \
+ "#mfc0\t$1, $16, 1\n\t" \
+ "#.set\tmips0\n\t" \
+ ".word\t0x40018001\n\t" \
+ "move\t%0,$1\n\t" \
+ ".set\tat\n\t" \
+ ".set\treorder" \
+ :"=r" (__res)); \
+ __res;})
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc1\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbp\n\t"
+ ".set pop");
+}
+
+static inline void tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbr\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwi\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwr\n\t"
+ ".set pop");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+
+static inline unsigned long get_pagemask(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $5\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_pagemask(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $5\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && !defined(CONFIG_CPU_MIPS32)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space.
+ */
+static inline void set_entrylo0(unsigned long long val)
+{
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ "dsll\t%M0, %M0, 32\n\t"
+ "or\t%L0, %L0, %M0\n\t"
+ "dmtc0\t%L0, $2\n\t"
+ ".set\tmips0"
+ : : "r" (val));
+ __restore_flags(flags);
+}
+
+static inline void set_entrylo1(unsigned long long val)
+{
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ "dsll\t%M0, %M0, 32\n\t"
+ "or\t%L0, %L0, %M0\n\t"
+ "dmtc0\t%L0, $3\n\t"
+ ".set\tmips0"
+ : : "r" (val));
+ __restore_flags(flags);
+}
+
+static inline unsigned long long get_entrylo0(void)
+{
+ unsigned long flags, val;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dmfc0\t%M0, $2\n\t"
+ "dsll\t%L0, %M0, 32\n\t"
+ "dsrl\t%M0, %M0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ ".set\tmips0"
+ : "=r" (val));
+ __restore_flags(flags);
+
+ return val;
+}
+
+static inline unsigned long long get_entrylo1(void)
+{
+ unsigned long flags, val;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dmfc0\t%M0, $3\n\t"
+ "dsrl\t%L0, %M0, 32\n\t"
+ "dsrl\t%M0, %M0, 32\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ ".set\tmips0"
+ : "=r" (val));
+ __restore_flags(flags);
+
+ return val;
+}
+
+#else
+
+static inline void set_entrylo0(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $2\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $3\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo0(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $2\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
+}
+
+static inline unsigned long get_entrylo1(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $3\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
+}
+
+#endif
+
+/* CP0_ENTRYHI register */
+static inline unsigned long get_entryhi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $10\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entryhi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $10\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_INDEX register */
+static inline unsigned long get_index(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $0\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_index(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $0\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_WIRED register */
+static inline unsigned long get_wired(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $6\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_wired(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $6\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_STATUS register */
+static inline unsigned int get_status(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $12\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_status(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $12\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_info(void)
+{
+ unsigned long val;
+
+ __asm__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $7\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+static inline unsigned long get_taglo(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $28\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taglo(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $28\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_taghi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $29\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taghi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $29\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_context(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $4\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_context(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $4\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_errorepc(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $30\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_errorepc(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $30\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register) \
+static inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#define __enable_fpu() \
+do { \
+ set_cp0_status(ST0_CU1); \
+ asm("nop;nop;nop;nop"); /* max. hazard */ \
+} while (0)
+
+#define __disable_fpu() \
+do { \
+ clear_cp0_status(ST0_CU1); \
+ /* We don't care about the cp0 hazard here */ \
+} while (0)
+
+#define enable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __enable_fpu(); \
+} while (0)
+
+#define disable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __disable_fpu(); \
+} while (0)
+
+#endif /* !__ASSEMBLY__ */
+
#endif /* _ASM_MIPSREGS_H */
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)