patch-2.4.19 linux-2.4.19/arch/mips64/kernel/traps.c
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- Lines: 688
- Date:
Fri Aug 2 17:39:43 2002
- Orig file:
linux-2.4.18/arch/mips64/kernel/traps.c
- Orig date:
Sun Sep 9 10:43:01 2001
diff -urN linux-2.4.18/arch/mips64/kernel/traps.c linux-2.4.19/arch/mips64/kernel/traps.c
@@ -7,25 +7,30 @@
* Copyright (C) 1995, 1996 Paul M. Antoine
* Copyright (C) 1998 Ulf Carlsson
* Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Maciej W. Rozycki
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
+#include <linux/module.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/spinlock.h>
+#include <asm/bootinfo.h>
#include <asm/branch.h>
-#include <asm/cachectl.h>
+#include <asm/cpu.h>
+#include <asm/module.h>
#include <asm/pgtable.h>
#include <asm/io.h>
-#include <asm/bootinfo.h>
#include <asm/ptrace.h>
#include <asm/watch.h>
#include <asm/system.h>
+#include <asm/traps.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
+#include <asm/cachectl.h>
extern asmlinkage void __xtlb_mod(void);
extern asmlinkage void __xtlb_tlbl(void);
@@ -42,14 +47,16 @@
extern asmlinkage void handle_tr(void);
extern asmlinkage void handle_fpe(void);
extern asmlinkage void handle_watch(void);
+extern asmlinkage void handle_mcheck(void);
extern asmlinkage void handle_reserved(void);
-static char *cpu_names[] = CPU_NAMES;
+extern int fpu_emulator_cop1Handler(struct pt_regs *);
+void fpu_emulator_init_fpu(void);
char watch_available = 0;
char dedicated_iv_available = 0;
-char vce_available = 0;
-char mips4_available = 0;
+
+int (*be_board_handler)(struct pt_regs *regs, int is_fixup);
int kstack_depth_to_print = 24;
@@ -110,7 +117,7 @@
printk("\nCall Trace:");
- while ((unsigned long) stack & (PAGE_SIZE -1)) {
+ while ((unsigned long) stack & (PAGE_SIZE - 1)) {
unsigned long addr;
if (__get_user(addr, stack++)) {
@@ -143,6 +150,12 @@
}
}
+void show_trace_task(struct task_struct *tsk)
+{
+ show_trace((unsigned long *)tsk->thread.reg29);
+}
+
+
void show_code(unsigned int *pc)
{
long i;
@@ -159,16 +172,60 @@
}
}
-spinlock_t die_lock;
+void show_regs(struct pt_regs *regs)
+{
+ printk("Cpu %d\n", smp_processor_id());
+ /* Saved main processor registers. */
+ printk("$0 : %016lx %016lx %016lx %016lx\n",
+ 0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
+ printk("$4 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
+ printk("$8 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
+ printk("$12 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
+ printk("$16 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
+ printk("$20 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
+ printk("$24 : %016lx %016lx\n",
+ regs->regs[24], regs->regs[25]);
+ printk("$28 : %016lx %016lx %016lx %016lx\n",
+ regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
+ printk("Hi : %016lx\n", regs->hi);
+ printk("Lo : %016lx\n", regs->lo);
+
+ /* Saved cp0 registers. */
+ printk("epc : %016lx %s\nbadvaddr: %016lx\n",
+ regs->cp0_epc, print_tainted(), regs->cp0_badvaddr);
+ printk("Status : %08x [ ", (unsigned int) regs->cp0_status);
+ if (regs->cp0_status & ST0_KX) printk("KX ");
+ if (regs->cp0_status & ST0_SX) printk("SX ");
+ if (regs->cp0_status & ST0_UX) printk("UX ");
+ switch (regs->cp0_status & ST0_KSU) {
+ case KSU_USER: printk("USER "); break;
+ case KSU_SUPERVISOR: printk("SUPERVISOR "); break;
+ case KSU_KERNEL: printk("KERNEL "); break;
+ default: printk("BAD_MODE "); break;
+ }
+ if (regs->cp0_status & ST0_ERL) printk("ERL ");
+ if (regs->cp0_status & ST0_EXL) printk("EXL ");
+ if (regs->cp0_status & ST0_IE) printk("IE ");
+ printk("]\n");
+
+ printk("Cause : %08x\n", (unsigned int) regs->cp0_cause);
+}
+
+static spinlock_t die_lock;
-void die(const char * str, struct pt_regs * regs, unsigned long err)
+void die(const char * str, struct pt_regs * regs)
{
if (user_mode(regs)) /* Just return if in user mode. */
return;
console_verbose();
spin_lock_irq(&die_lock);
- printk("%s: %04lx\n", str, err & 0xffff);
+ printk("%s\n", str);
show_regs(regs);
printk("Process %s (pid: %d, stackpage=%08lx)\n",
current->comm, current->pid, (unsigned long) current);
@@ -180,82 +237,178 @@
do_exit(SIGSEGV);
}
-void die_if_kernel(const char * str, struct pt_regs * regs, unsigned long err)
+void die_if_kernel(const char * str, struct pt_regs * regs)
{
if (!user_mode(regs))
- die(str, regs, err);
+ die(str, regs);
}
-void do_ov(struct pt_regs *regs)
+extern const struct exception_table_entry __start___dbe_table[];
+extern const struct exception_table_entry __stop___dbe_table[];
+
+void __declare_dbe_table(void)
{
- if (compute_return_epc(regs))
- return;
- force_sig(SIGFPE, current);
+ __asm__ __volatile__(
+ ".section\t__dbe_table,\"a\"\n\t"
+ ".previous"
+ );
}
-#ifdef CONFIG_MIPS_FPE_MODULE
-static void (*fpe_handler)(struct pt_regs *regs, unsigned int fcr31);
+static inline unsigned long
+search_one_table(const struct exception_table_entry *first,
+ const struct exception_table_entry *last,
+ unsigned long value)
+{
+ const struct exception_table_entry *mid;
+ long diff;
-/*
- * Register_fpe/unregister_fpe are for debugging purposes only. To make
- * this hack work a bit better there is no error checking.
- */
-int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31))
+ while (first < last) {
+ mid = (last - first) / 2 + first;
+ diff = mid->insn - value;
+ if (diff < 0)
+ first = mid + 1;
+ else
+ last = mid;
+ }
+ return (first == last && first->insn == value) ? first->nextinsn : 0;
+}
+
+extern spinlock_t modlist_lock;
+
+static inline unsigned long
+search_dbe_table(unsigned long addr)
{
- fpe_handler = handler;
- return 0;
+ unsigned long ret = 0;
+
+#ifndef CONFIG_MODULES
+ /* There is only the kernel to search. */
+ ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
+ return ret;
+#else
+ unsigned long flags;
+
+ /* The kernel is the last "module" -- no need to treat it special. */
+ struct module *mp;
+ struct archdata *ap;
+
+ spin_lock_irqsave(&modlist_lock, flags);
+ for (mp = module_list; mp != NULL; mp = mp->next) {
+ if (!mod_member_present(mp, archdata_end) ||
+ !mod_archdata_member_present(mp, struct archdata,
+ dbe_table_end))
+ continue;
+ ap = (struct archdata *)(mp->archdata_start);
+
+ if (ap->dbe_table_start == NULL ||
+ !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING)))
+ continue;
+ ret = search_one_table(ap->dbe_table_start,
+ ap->dbe_table_end - 1, addr);
+ if (ret)
+ break;
+ }
+ spin_unlock_irqrestore(&modlist_lock, flags);
+ return ret;
+#endif
}
-int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31))
+asmlinkage void do_be(struct pt_regs *regs)
{
- fpe_handler = NULL;
- return 0;
+ unsigned long new_epc;
+ unsigned long fixup = 0;
+ int data = regs->cp0_cause & 4;
+ int action = MIPS_BE_FATAL;
+
+ if (data && !user_mode(regs))
+ fixup = search_dbe_table(regs->cp0_epc);
+
+ if (fixup)
+ action = MIPS_BE_FIXUP;
+
+ if (be_board_handler)
+ action = be_board_handler(regs, fixup != 0);
+
+ switch (action) {
+ case MIPS_BE_DISCARD:
+ return;
+ case MIPS_BE_FIXUP:
+ if (fixup) {
+ new_epc = fixup_exception(dpf_reg, fixup,
+ regs->cp0_epc);
+ regs->cp0_epc = new_epc;
+ return;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /*
+ * Assume it would be too dangerous to continue ...
+ */
+ printk(KERN_ALERT "%s bus error, epc == %08lx, ra == %08lx\n",
+ data ? "Data" : "Instruction",
+ regs->cp0_epc, regs->regs[31]);
+ die_if_kernel("Oops", regs);
+ force_sig(SIGBUS, current);
+}
+
+void do_ov(struct pt_regs *regs)
+{
+ if (compute_return_epc(regs))
+ return;
+ force_sig(SIGFPE, current);
}
-#endif
/*
* XXX Delayed fp exceptions when doing a lazy ctx switch XXX
*/
-void do_fpe(struct pt_regs *regs, unsigned long fcr31)
+asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
{
- unsigned long pc;
- unsigned int insn;
- extern void simfp(unsigned int);
-
-#ifdef CONFIG_MIPS_FPE_MODULE
- if (fpe_handler != NULL) {
- fpe_handler(regs, fcr31);
- return;
- }
-#endif
- if (fcr31 & 0x20000) {
- /* Retry instruction with flush to zero ... */
- if (!(fcr31 & (1<<24))) {
- printk("Setting flush to zero for %s.\n",
- current->comm);
- fcr31 &= ~0x20000;
- fcr31 |= (1<<24);
- __asm__ __volatile__(
- "ctc1\t%0,$31"
- : /* No outputs */
- : "r" (fcr31));
- return;
- }
- pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);
- if (get_user(insn, (unsigned int *)pc)) {
- /* XXX Can this happen? */
- force_sig(SIGSEGV, current);
+ if (fcr31 & FPU_CSR_UNI_X) {
+ int sig;
+
+ /*
+ * Unimplemented operation exception. If we've got the full
+ * software emulator on-board, let's use it...
+ *
+ * Force FPU to dump state into task/thread context. We're
+ * moving a lot of data here for what is probably a single
+ * instruction, but the alternative is to pre-decode the FP
+ * register operands before invoking the emulator, which seems
+ * a bit extreme for what should be an infrequent event.
+ */
+ save_fp(current);
+
+ /* Run the emulator */
+ sig = fpu_emulator_cop1Handler(regs);
+
+ /*
+ * We can't allow the emulated instruction to leave any of
+ * the cause bit set in $fcr31.
+ */
+ current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X;
+
+ /* Restore the hardware register state */
+ restore_fp(current);
+
+ /* If something went wrong, signal */
+ if (sig)
+ {
+ /*
+ * Return EPC is not calculated in the FPU emulator,
+ * if a signal is being send. So we calculate it here.
+ */
+ compute_return_epc(regs);
+ force_sig(sig, current);
}
- printk(KERN_DEBUG "Unimplemented exception for insn %08x at 0x%08lx in %s.\n",
- insn, regs->cp0_epc, current->comm);
- simfp(insn);
+ return;
}
if (compute_return_epc(regs))
return;
- //force_sig(SIGFPE, current);
- printk(KERN_DEBUG "Should send SIGFPE to %s\n", current->comm);
+ force_sig(SIGFPE, current);
}
void do_bp(struct pt_regs *regs)
@@ -291,7 +444,7 @@
info.si_code = FPE_INTOVF;
info.si_signo = SIGFPE;
info.si_errno = 0;
- info.si_addr = (void *)compute_return_epc(regs);
+ info.si_addr = (void *)regs->cp0_epc;
force_sig_info(SIGFPE, &info, current);
break;
default:
@@ -333,7 +486,7 @@
info.si_code = FPE_INTOVF;
info.si_signo = SIGFPE;
info.si_errno = 0;
- info.si_addr = (void *)compute_return_epc(regs);
+ info.si_addr = (void *)regs->cp0_epc;
force_sig_info(SIGFPE, &info, current);
break;
default:
@@ -347,24 +500,35 @@
void do_ri(struct pt_regs *regs)
{
- printk("Cpu%d[%s:%d] Illegal instruction at %08lx ra=%08lx\n",
- smp_processor_id(), current->comm, current->pid, regs->cp0_epc,
- regs->regs[31]);
if (compute_return_epc(regs))
return;
+
force_sig(SIGILL, current);
}
void do_cpu(struct pt_regs *regs)
{
u32 cpid;
+ int sig;
cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
if (cpid != 1)
goto bad_cid;
+ if (!(mips_cpu.options & MIPS_CPU_FPU))
+ goto fp_emul;
+
regs->cp0_status |= ST0_CU1;
-#ifndef CONFIG_SMP
+
+#ifdef CONFIG_SMP
+ if (current->used_math) {
+ lazy_fpu_switch(0, current);
+ } else {
+ init_fpu();
+ current->used_math = 1;
+ }
+ current->flags |= PF_USEDFPU;
+#else
if (last_task_used_math == current)
return;
@@ -376,18 +540,28 @@
current->used_math = 1;
}
last_task_used_math = current;
-#else
- if (current->used_math) {
- lazy_fpu_switch(0, current);
- } else {
- init_fpu();
+#endif
+ return;
+
+fp_emul:
+ if (!current->used_math) {
+ fpu_emulator_init_fpu();
current->used_math = 1;
}
- current->flags |= PF_USEDFPU;
-#endif
+ sig = fpu_emulator_cop1Handler(regs);
+ if (sig)
+ {
+ /*
+ * Return EPC is not calculated in the FPU emulator, if
+ * a signal is being send. So we calculate it here.
+ */
+ compute_return_epc(regs);
+ force_sig(sig, current);
+ }
return;
bad_cid:
+ compute_return_epc(regs);
force_sig(SIGILL, current);
}
@@ -401,6 +575,13 @@
panic("Caught WATCH exception - probably caused by stack overflow.");
}
+asmlinkage void do_mcheck(struct pt_regs *regs)
+{
+ show_regs(regs);
+ panic("Caught Machine Check exception - probably caused by multiple "
+ "matching entries in the TLB.");
+}
+
void do_reserved(struct pt_regs *regs)
{
/*
@@ -430,23 +611,6 @@
}
}
-/*
- * Some MIPS CPUs have a dedicated interrupt vector which reduces the
- * interrupt processing overhead. Use it where available.
- * FIXME: more CPUs than just the Nevada have this feature.
- */
-static inline void setup_dedicated_int(void)
-{
- extern void except_vec4(void);
-
- switch(mips_cputype) {
- case CPU_NEVADA:
- memcpy((void *)(KSEG0 + 0x200), except_vec4, 8);
- set_cp0_cause(CAUSEF_IV, CAUSEF_IV);
- dedicated_iv_available = 1;
- }
-}
-
unsigned long exception_handlers[32];
/*
@@ -458,33 +622,32 @@
{
unsigned long handler = (unsigned long) addr;
exception_handlers[n] = handler;
- if (n == 0 && dedicated_iv_available) {
+
+ if (n == 0 && mips_cpu.options & MIPS_CPU_DIVEC) {
*(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
(0x03ffffff & (handler >> 2));
flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
}
}
-static inline void mips4_setup(void)
+void __init per_cpu_trap_init(void)
{
- switch (mips_cputype) {
- case CPU_R5000:
- case CPU_R5000A:
- case CPU_NEVADA:
- case CPU_R8000:
- case CPU_R10000:
- mips4_available = 1;
- set_cp0_status(ST0_XX, ST0_XX);
- }
-}
+ unsigned int cpu = smp_processor_id();
-static inline void go_64(void)
-{
- unsigned int bits;
+ /* Some firmware leaves the BEV flag set, clear it. */
+ clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV);
+ set_cp0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX);
+
+ /*
+ * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+ * interrupt processing overhead. Use it where available.
+ */
+ if (mips_cpu.options & MIPS_CPU_DIVEC)
+ set_cp0_cause(CAUSEF_IV);
- bits = ST0_KX|ST0_SX|ST0_UX;
- set_cp0_status(bits, bits);
- printk("Entering 64-bit mode.\n");
+ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+ set_context(((long)(&pgd_current[cpu])) << 23);
+ set_wired(0);
}
void __init trap_init(void)
@@ -493,13 +656,13 @@
extern char except_vec1_r10k;
extern char except_vec2_generic;
extern char except_vec3_generic, except_vec3_r4000;
- extern void bus_error_init(void);
+ extern char except_vec4;
unsigned long i;
+ int dummy;
- /* Some firmware leaves the BEV flag set, clear it. */
- set_cp0_status(ST0_BEV, 0);
+ per_cpu_trap_init();
- /* Copy the generic exception handler code to it's final destination. */
+ /* Copy the generic exception handlers to their final destination. */
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
@@ -513,30 +676,47 @@
* Only some CPUs have the watch exceptions or a dedicated
* interrupt vector.
*/
- watch_init(mips_cputype);
- setup_dedicated_int();
- mips4_setup();
- go_64(); /* In memoriam C128 ;-) */
+ watch_init(mips_cpu.cputype);
+
+ /*
+ * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+ * interrupt processing overhead. Use it where available.
+ */
+ memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
+
+ if (mips_cpu.options & MIPS_CPU_MCHECK)
+ set_except_vector(24, handle_mcheck);
+
+ /*
+ * The Data Bus Errors / Instruction Bus Errors are signaled
+ * by external hardware. Therefore these two exceptions
+ * may have board specific handlers.
+ */
+ bus_error_init();
/*
* Handling the following exceptions depends mostly of the cpu type
*/
- switch(mips_cputype) {
- case CPU_R10000:
- /*
- * The R10000 is in most aspects similar to the R4400. It
- * should get some special optimizations.
- */
- write_32bit_cp0_register(CP0_FRAMEMASK, 0);
- set_cp0_status(ST0_XX, ST0_XX);
- goto r4k;
+ switch(mips_cpu.cputype) {
+ case CPU_SB1:
+#ifdef CONFIG_SB1_CACHE_ERROR
+ {
+ /* Special cache error handler for SB1 */
+ extern char except_vec2_sb1;
+ memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80);
+ memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80);
+ }
+#endif
+ /* Enable timer interrupt and scd mapped interrupt */
+ clear_cp0_status(0xf000);
+ set_cp0_status(0xc00);
+ /* Fall through. */
+ case CPU_R10000:
case CPU_R4000MC:
case CPU_R4400MC:
case CPU_R4000SC:
case CPU_R4400SC:
- vce_available = 1;
- /* Fall through ... */
case CPU_R4000PC:
case CPU_R4400PC:
case CPU_R4200:
@@ -544,20 +724,16 @@
case CPU_R4600:
case CPU_R5000:
case CPU_NEVADA:
-r4k:
/* Debug TLB refill handler. */
memcpy((void *)KSEG0, &except_vec0, 0x80);
memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
- /* Cache error vector */
- memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
-
- if (vce_available) {
+ if (mips_cpu.options & MIPS_CPU_VCE) {
memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
- 0x180);
+ 0x80);
} else {
memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
- 0x100);
+ 0x80);
}
set_except_vector(1, __xtlb_mod);
@@ -566,8 +742,8 @@
set_except_vector(4, handle_adel);
set_except_vector(5, handle_ades);
- /* DBE / IBE exception handler are system specific. */
- bus_error_init();
+ set_except_vector(6, handle_ibe);
+ set_except_vector(7, handle_dbe);
set_except_vector(8, handle_sys);
set_except_vector(9, handle_bp);
@@ -579,7 +755,7 @@
break;
case CPU_R8000:
- panic("unsupported CPU type %s.\n", cpu_names[mips_cputype]);
+ panic("R8000 is unsupported");
break;
case CPU_UNKNOWN:
@@ -588,6 +764,9 @@
}
flush_icache_range(KSEG0, KSEG0 + 0x200);
+ if (mips_cpu.isa_level == MIPS_CPU_ISA_IV)
+ set_cp0_status(ST0_XX);
+
atomic_inc(&init_mm.mm_count); /* XXX UP? */
current->active_mm = &init_mm;
}
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