patch-2.3.40 linux/include/asm-i386/smp.h

• Lines: 256
• Date: Thu Jan 20 16:05:30 2000
• Orig file: v2.3.39/linux/include/asm-i386/smp.h
• Orig date: Tue Dec 7 09:32:49 1999

diff -u --recursive --new-file v2.3.39/linux/include/asm-i386/smp.h linux/include/asm-i386/smp.h
@@ -4,228 +4,64 @@
 /*
  * We need the APIC definitions automatically as part of 'smp.h'
  */
+#ifndef ASSEMBLY
 #include <linux/config.h>
+#include <linux/threads.h>
+#include <linux/ptrace.h>
+#endif
+
 #ifdef CONFIG_X86_LOCAL_APIC
 #ifndef ASSEMBLY
 #include <asm/fixmap.h>
-#include <asm/apic.h>
 #include <asm/bitops.h>
+#include <asm/mpspec.h>
+#include <asm/io_apic.h>
+#include <asm/apic.h>
 #endif
 #endif
 
-#ifdef __SMP__
+#ifdef CONFIG_SMP
 #ifndef ASSEMBLY
 
-#include <linux/threads.h>
-#include <linux/ptrace.h>
-
 /*
- *	Support definitions for SMP machines following the intel multiprocessing
- *	specification
- */
-
-/*
- *	This tag identifies where the SMP configuration
- *	information is. 
+ * Private routines/data
  */
  
-#define SMP_MAGIC_IDENT	(('_'<<24)|('P'<<16)|('M'<<8)|'_')
-
-struct intel_mp_floating
-{
-	char mpf_signature[4];		/* "_MP_" 			*/
-	unsigned long mpf_physptr;	/* Configuration table address	*/
-	unsigned char mpf_length;	/* Our length (paragraphs)	*/
-	unsigned char mpf_specification;/* Specification version	*/
-	unsigned char mpf_checksum;	/* Checksum (makes sum 0)	*/
-	unsigned char mpf_feature1;	/* Standard or configuration ? 	*/
-	unsigned char mpf_feature2;	/* Bit7 set for IMCR|PIC	*/
-	unsigned char mpf_feature3;	/* Unused (0)			*/
-	unsigned char mpf_feature4;	/* Unused (0)			*/
-	unsigned char mpf_feature5;	/* Unused (0)			*/
-};
-
-struct mp_config_table
-{
-	char mpc_signature[4];
-#define MPC_SIGNATURE "PCMP"
-	unsigned short mpc_length;	/* Size of table */
-	char  mpc_spec;			/* 0x01 */
-	char  mpc_checksum;
-	char  mpc_oem[8];
-	char  mpc_productid[12];
-	unsigned long mpc_oemptr;	/* 0 if not present */
-	unsigned short mpc_oemsize;	/* 0 if not present */
-	unsigned short mpc_oemcount;
-	unsigned long mpc_lapic;	/* APIC address */
-	unsigned long reserved;
-};
-
-/* Followed by entries */
-
-#define	MP_PROCESSOR	0
-#define	MP_BUS		1
-#define	MP_IOAPIC	2
-#define	MP_INTSRC	3
-#define	MP_LINTSRC	4
-
-struct mpc_config_processor
-{
-	unsigned char mpc_type;
-	unsigned char mpc_apicid;	/* Local APIC number */
-	unsigned char mpc_apicver;	/* Its versions */
-	unsigned char mpc_cpuflag;
-#define CPU_ENABLED		1	/* Processor is available */
-#define CPU_BOOTPROCESSOR	2	/* Processor is the BP */
-	unsigned long mpc_cpufeature;		
-#define CPU_STEPPING_MASK 0x0F
-#define CPU_MODEL_MASK	0xF0
-#define CPU_FAMILY_MASK	0xF00
-	unsigned long mpc_featureflag;	/* CPUID feature value */
-	unsigned long mpc_reserved[2];
-};
-
-struct mpc_config_bus
-{
-	unsigned char mpc_type;
-	unsigned char mpc_busid;
-	unsigned char mpc_bustype[6] __attribute((packed));
-};
-
-#define BUSTYPE_EISA	"EISA"
-#define BUSTYPE_ISA	"ISA"
-#define BUSTYPE_INTERN	"INTERN"	/* Internal BUS */
-#define BUSTYPE_MCA	"MCA"
-#define BUSTYPE_VL	"VL"		/* Local bus */
-#define BUSTYPE_PCI	"PCI"
-#define BUSTYPE_PCMCIA	"PCMCIA"
-
-/* We don't understand the others */
-
-struct mpc_config_ioapic
-{
-	unsigned char mpc_type;
-	unsigned char mpc_apicid;
-	unsigned char mpc_apicver;
-	unsigned char mpc_flags;
-#define MPC_APIC_USABLE		0x01
-	unsigned long mpc_apicaddr;
-};
-
-struct mpc_config_intsrc
-{
-	unsigned char mpc_type;
-	unsigned char mpc_irqtype;
-	unsigned short mpc_irqflag;
-	unsigned char mpc_srcbus;
-	unsigned char mpc_srcbusirq;
-	unsigned char mpc_dstapic;
-	unsigned char mpc_dstirq;
-};
-
-enum mp_irq_source_types {
-	mp_INT = 0,
-	mp_NMI = 1,
-	mp_SMI = 2,
-	mp_ExtINT = 3
-};
-
-#define MP_IRQDIR_DEFAULT	0
-#define MP_IRQDIR_HIGH		1
-#define MP_IRQDIR_LOW		3
-
-
-struct mpc_config_lintsrc
-{
-	unsigned char mpc_type;
-	unsigned char mpc_irqtype;
-	unsigned short mpc_irqflag;
-	unsigned char mpc_srcbusid;
-	unsigned char mpc_srcbusirq;
-	unsigned char mpc_destapic;	
-#define MP_APIC_ALL	0xFF
-	unsigned char mpc_destapiclint;
-};
-
-
-/*
- *	Default configurations
- *
- *	1	2 CPU ISA 82489DX
- *	2	2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
- *	3	2 CPU EISA 82489DX
- *	4	2 CPU MCA 82489DX
- *	5	2 CPU ISA+PCI
- *	6	2 CPU EISA+PCI
- *	7	2 CPU MCA+PCI
- */
-
-/*
- *	Private routines/data
- */
- 
-extern int smp_found_config;
-extern void init_smp_config(void);
-extern void init_smp_mappings(void);
 extern void smp_alloc_memory(void);
-extern unsigned long cpu_present_map;
+extern unsigned long phys_cpu_present_map;
 extern unsigned long cpu_online_map;
 extern volatile unsigned long smp_invalidate_needed;
 extern int pic_mode;
 extern void smp_flush_tlb(void);
-extern int get_maxlvt(void);
-extern void disable_local_APIC (void);
 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
 extern void smp_send_reschedule(int cpu);
 extern void smp_invalidate_rcv(void);		/* Process an NMI */
-extern void smp_local_timer_interrupt(struct pt_regs * regs);
 extern void (*mtrr_hook) (void);
-extern void setup_APIC_clocks(void);
 extern void zap_low_mappings (void);
-extern volatile int cpu_number_map[NR_CPUS];
-extern volatile int __cpu_logical_map[NR_CPUS];
-extern inline int cpu_logical_map(int cpu)
-{
-	return __cpu_logical_map[cpu];
-}
 
-extern __inline void apic_write(unsigned long reg, unsigned long v)
+/*
+ * On x86 all CPUs are mapped 1:1 to the APIC space.
+ * This simplifies scheduling and IPI sending and
+ * compresses data structures.
+ */
+extern inline int cpu_logical_map(int cpu)
 {
-	*((volatile unsigned long *)(APIC_BASE+reg))=v;
+	return cpu;
 }
-
-extern __inline unsigned long apic_read(unsigned long reg)
+extern inline int cpu_number_map(int cpu)
 {
-	return *((volatile unsigned long *)(APIC_BASE+reg));
+	return cpu;
 }
 
-extern unsigned int apic_timer_irqs [NR_CPUS];
-
-#ifdef CONFIG_X86_GOOD_APIC
-# define FORCE_READ_AROUND_WRITE 0
-# define apic_readaround(x)
-#else
-# define FORCE_READ_AROUND_WRITE 1
-# define apic_readaround(x) apic_read(x)
-#endif
-
-#define apic_write_around(x,y) \
-		do { apic_readaround(x); apic_write(x,y); } while (0)
-
-extern inline void ack_APIC_irq(void)
-{
-        /* Clear the IPI */
-
-	apic_readaround(APIC_EOI);
-	/*
-	 * on P6+ cores (CONFIG_X86_GOOD_APIC) ack_APIC_irq() actually
-	 * gets compiled as a single instruction ... yummie.
-	 */
-        apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */
-}
+/*
+ * Some lowlevel functions might want to know about
+ * the real APIC ID <-> CPU # mapping.
+ */
+extern volatile int x86_apicid_to_cpu[NR_CPUS];
+extern volatile int x86_cpu_to_apicid[NR_CPUS];
 
 /*
- *	General functions that each host system must provide.
+ * General functions that each host system must provide.
  */
  
 extern void smp_boot_cpus(void);