patch-1.3.87 linux/Documentation/smp.tex

• Lines: 100
• Date: Fri Apr 12 09:49:29 1996
• Orig file: v1.3.86/linux/Documentation/smp.tex
• Orig date: Fri Feb 9 16:59:04 1996

diff -u --recursive --new-file v1.3.86/linux/Documentation/smp.tex linux/Documentation/smp.tex
@@ -37,7 +37,7 @@
 The Intel pentium processors have a wide variety of inbuilt facilities for 
 supporting multiprocessing, including hardware cache coherency, built in 
 interprocessor interrupt handling and a set of atomic test and set, 
-exchange and similar operations. The cache coherency in paticular makes the 
+exchange and similar operations. The cache coherency in particular makes the 
 operating systems job far easier.
 
 The specification defines a detailed configuration structure in ROM that 
@@ -82,8 +82,8 @@
 and only the processor holding the lock may handle an interrupt.
 
 Such a choice is however poor for performance. In the longer term it is 
-neccessary to move to finer grained parallelisn in order to get the best 
-system performance. This can be done heirarchically by gradually refining 
+necessary to move to finer grained parallelism in order to get the best 
+system performance. This can be done hierarchically by gradually refining 
 the locks to cover smaller areas. With the current kernel highly CPU bound 
 process sets perform well but I/O bound task sets can easily degenerate to 
 near single processor performance levels. This refinement will be needed to 
@@ -91,7 +91,7 @@
 
 \subsection{Changes To The Portable Kernel Components}
 The kernel changes are split into generic SMP support changes and 
-architecture specific changes neccessary to accomodate each different 
+architecture specific changes necessary to accommodate each different 
 processor type Linux is ported to.
 
 
@@ -129,7 +129,7 @@
 
 which does any final setup and then spins the processor while the boot 
 up processor forks off enough idle threads for each processor. This is 
-neccessary because the scheduler assumes there is always something to run. 
+necessary because the scheduler assumes there is always something to run. 
 Having generated these threads and forked init the architecture specific 
 
 {\tt \bf void smp\_commence(void)}
@@ -162,19 +162,19 @@
 
 The fork system call is modified to generate multiple processes with a 
 process id of zero until the SMP kernel starts up properly. This is 
-neccessary because process number 1 must be init, and it is desirable that 
+necessary because process number 1 must be init, and it is desirable that 
 all the system threads are process 0. 
 
 The final area within the scheduling of processes that does cause problems 
 is the fact the uniprocessor kernel hard codes tests for the idle threads 
 as task[0] and the init process as task[1]. Because there are multiple idle 
-threads it is neccessary to replace these with tests that the process id is 
+threads it is necessary to replace these with tests that the process id is 
 0 and a search for process ID 1, respectively.
 
 \subsubsection{Memory Management}
 The memory management core of the existing Linux system functions 
 adequately within the multiprocessor framework providing the locking is 
-used. Certain processor specific areas do need changing, in paticular 
+used. Certain processor specific areas do need changing, in particular 
 invalidate() must invalidate the TLB's of all processors before it returns.
 
 
@@ -224,7 +224,7 @@
 
 In the initialisation done by the first processor the arch/i386/mm/init 
 code is modified to scan the low page, top page and BIOS for intel MP 
-signature blocks. This is neccessary because the MP signature blocks must 
+signature blocks. This is necessary because the MP signature blocks must 
 be read and processed before the kernel is allowed to allocate and destroy 
 the page at the top of low memory. Having established the number of 
 processors it reserves a set of pages to provide a stack come boot up area 
@@ -257,7 +257,7 @@
 
 \subsubsection{Message Handling and Support Code}
 The architecture specific code implements the smp\_processor\_id() function 
-by querying the APIC logical identity register. Because the APIC isnt 
+by querying the APIC logical identity register. Because the APIC isn't 
 mapped into the kernel address space at boot, the initial value returned is 
 rigged by setting the APIC base pointer to point at a suitable constant. 
 Once the system starts doing the SMP setup (in smp\_boot\_cpus()), the APIC 
@@ -267,7 +267,7 @@
 
 Message passing is accomplished using a pair of IPI's on interrupt 13 
 (unused by the 80486 FPU's in SMP mode) and interrupt 16. Two are used in 
-order to seperate messages that cannot be processed until the receiver 
+order to separate messages that cannot be processed until the receiver 
 obtains the kernel spinlock from messages that can be processed 
 immediately. In effect IRQ 13 is a fast IRQ handler that does not obtain 
 the locks, and cannot cause a reschedule, while IRQ 16 is a slow IRQ that 
@@ -312,9 +312,9 @@
 as an emulation of the traditional PC interrupt controllers when the 
 machine boots (so that an Intel MP machine boots one CPU and PC 
 compatible). The kernel has all the relevant locks but does not yet 
-reprogram the 82489 to deliver interrupts to arbitary processors as it 
+reprogram the 82489 to deliver interrupts to arbitrary processors as it 
 should. This requires further modification of the standard Linux interrupt 
-handling code, and is paticularly messy as the interrupt handler behaviour 
+handling code, and is particularly messy as the interrupt handler behaviour 
 has to change as soon as the 82489 is switched into SMP mode.